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1.发明授权ESD protection using a capacitivly-coupled clamp for protecting low-voltage core transistors from high-voltage outputs 有权使用电容耦合钳位保护低压核心晶体管免受高压输出的ESD保护公开(公告)号：US08072721B2
公开(公告)日：2011-12-06
申请号：US12481696
申请日：2009-06-10
IPC分类号： H02H9/00
CPC分类号： H03K19/00315 , H01L27/0266 , H03K19/018557
摘要： An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor.
摘要翻译： 静电放电（ESD）保护电路保护核心晶体管。 n沟道输出晶体管的栅极的内部节点连接到n沟道栅极 - 接地晶体管的漏极到地。 栅极接地晶体管的栅极是通过ESD耦合电容器耦合到输出并由n沟道禁用晶体管和漏电阻器接地的耦合栅极节点。 n沟道禁用晶体管的栅极连接电源，并在供电时禁用ESD保护电路。 施加到输出端的ESD脉冲通过ESD耦合电容器耦合，使耦合栅极节点高电压，并接通栅极 - 接地晶体管，使n沟道输出晶体管的栅极接地，从而分解ESD电流。 防止ESD脉冲通过栅极接地晶体管的n沟道输出晶体管的寄生米勒电容器耦合。
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2.发明授权Constant-current control module using inverter filter multiplier for off-line current-mode primary-side sense isolated flyback converter 有权恒流控制模块采用变频器滤波器，用于离线电流模式初级侧感测隔离反激式转换器公开(公告)号：US08300431B2
公开(公告)日：2012-10-30
申请号：US12718707
申请日：2010-03-05
申请人： Chik Wai (David) Ng , Hing Kit Kwan , Po Wah (Patrick) Chang , Wai Kit (Victor) So , Kwok Kuen (David) Kwong
发明人： Chik Wai (David) Ng , Hing Kit Kwan , Po Wah (Patrick) Chang , Wai Kit (Victor) So , Kwok Kuen (David) Kwong
IPC分类号： H02M3/335
CPC分类号： H02M3/335
摘要： A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control.
摘要翻译： 回扫AC-DC电力转换器具有恒定电流控制回路，其感测变压器中的主要输出电流，以在没有昂贵的光隔离器的情况下控制次级输出。 初级侧控制电路可以使用准谐振（QR）或脉冲宽度调制（PWM）控制回路来切换通过变压器的一次电流的开和关。 将反馈电压与从初级电流回路感测的初级侧电压进行比较，以打开和关闭开关。 乘法器环路使用乘法器产生反馈电压。 电平移位反相器和低通滤波器通过将开关的占空比乘以反馈电压作为乘法器，以产生滤波电压。 高增益误差放大器将滤波电压与参考电压进行比较，以产生反馈电压。 乘法器产生二次电流和参考电压之间的简单关系，产生简化的电流控制。
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3.发明申请Constant-Current Control Module using Inverter Filter Multiplier for Off-line Current-Mode Primary-Side Sense Isolated Flyback Converter 有权恒流控制模块使用变频滤波乘法器进行离线电流模式初级侧检测隔离反激式转换器公开(公告)号：US20110216559A1
公开(公告)日：2011-09-08
申请号：US12718707
申请日：2010-03-05
IPC分类号： H02M3/335
CPC分类号： H02M3/335
摘要： A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control.
摘要翻译： 回扫AC-DC电力转换器具有恒定电流控制回路，其感测变压器中的主要输出电流，以在没有昂贵的光隔离器的情况下控制次级输出。 初级侧控制电路可以使用准谐振（QR）或脉冲宽度调制（PWM）控制回路来切换通过变压器的一次电流的开和关。 将反馈电压与从初级电流回路感测的初级侧电压进行比较，以打开和关闭开关。 乘法器环路使用乘法器产生反馈电压。 电平移位反相器和低通滤波器通过将开关的占空比乘以反馈电压作为乘法器，以产生滤波电压。 高增益误差放大器将滤波电压与参考电压进行比较，以产生反馈电压。 乘法器产生二次电流和参考电压之间的简单关系，产生简化的电流控制。
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4.发明申请Slew-Rate-Enhanced Error Amp with Adaptive Transconductance and Single Dominant Pole Shared by Main and Auxiliary Amps 有权具有自适应跨导和主主导极共同的主要和辅助放大器的转换率增益误差放大器公开(公告)号：US20100164625A1
公开(公告)日：2010-07-01
申请号：US12345862
申请日：2008-12-30
申请人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
发明人： Yat To (William) Wong , Chik Wai (David) Ng , Ho Ming (Karen) Wan , Kam Chuen Wan , Kwok Kuen (David) Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译： 误差放大器可用于控制功率调节晶体管。 误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。 输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。 当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。 通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。 主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。 串联晶体管增加了增益和输出阻抗。 在放大器中没有使用正反馈的情况下，可靠性提高。
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5.发明授权Low voltage high-output-driving CMOS voltage reference with temperature compensation 有权低电压高输出驱动CMOS电压基准，具有温度补偿功能公开(公告)号：US07705662B2
公开(公告)日：2010-04-27
申请号：US12237500
申请日：2008-09-25
IPC分类号： G05F3/02
CPC分类号： G05F3/30
摘要： A bandgap reference voltage generator has a first stage that generates a first current that is complementary-to-absolute-temperature (Ictat) and a second stage that generates a current that is proportional-to-absolute-temperature (Iptat). The Ictat and Iptat currents are both forced through a summing resistor to generate a voltage that is relatively independent of temperature, since the Ictat and Iptat currents cancel out each other's temperature dependencies. A PMOS output transistor drives current to an output load to maintain the load at the reference voltage. An op amp drives the gate of the PMOS output transistor and has inputs connected to emitters of PNP transistors in the second stage. A series of resistors generate the reference voltage between the PMOS output transistor and ground and drives bases of the PNP transistors and includes the summing resistor. Parasitic PNP transistors in an all-CMOS process are used. The generator operates with a 1-volt power supply.
摘要翻译： 带隙参考电压发生器具有产生互补绝对温度（Ictat）的第一电流的第一级和产生与绝对温度成比例的电流（Iptat）的第二级。 Ictat和Iptat电流都被强制通过求和电阻产生一个相对独立于温度的电压，因为Ictat和Iptat电流抵消了彼此的温度依赖性。 PMOS输出晶体管将电流驱动到输出负载以将负载保持在参考电压。 运算放大器驱动PMOS输出晶体管的栅极，并且在第二级中具有连接到PNP晶体管的发射极的输入。 一系列电阻器在PMOS输出晶体管和地之间产生参考电压，并驱动PNP晶体管的基极，并包含求和电阻。 使用全CMOS工艺中的寄生PNP晶体管。 发电机采用1伏电源供电。
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6.发明授权Output current estimation for an isolated flyback converter with variable switching frequency control and duty cycle adjustment for both PWM and PFM modes 有权用于PWM和PFM模式的具有可变开关频率控制和占空比调整的隔离反激式转换器的输出电流估计公开(公告)号：US08780590B2
公开(公告)日：2014-07-15
申请号：US13462986
申请日：2012-05-03
IPC分类号： H02M3/335
CPC分类号： H02M3/33507 , H02M2001/0009
摘要： A fly-back power converter has a current-estimating control loop that senses the primary output current in a transformer to control the secondary output. A primary-side control circuit switches primary current through the transformer on and off. A discharge time when a secondary current through an auxiliary winding of the transformer is flowing is generated by sampling a voltage divider on an auxiliary loop for a knee-point. A normalized duty cycle is calculated by multiplying the discharge time by a current that is proportional to the switching frequency and comparing to a sawtooth signal having the switching frequency. The peak of a primary-side voltage is sensed from the primary current loop and converted to a current and multiplied by the normalized duty cycle to generate an estimated current. An error amp compares the estimated current to a reference to adjust the oscillator frequency and peak current to control primary switching.
摘要翻译： 回扫功率转换器具有电流估算控制回路，其感测变压器中的主要输出电流以控制次级输出。 初级侧控制电路通过变压器开启和关闭一次电流。 通过变压器的辅助绕组的二次电流流过的放电时间是通过对用于拐点的辅助回路上的分压器进行采样而产生的。 通过将放电时间乘以与开关频率成比例的电流并与具有开关频率的锯齿波信号进行比较来计算归一化占空比。 初级侧电压的峰值从初级电流回路感测并转换为电流并乘以归一化的占空比以产生估计电流。 误差放大器将估计电流与参考值进行比较，以调整振荡器频率和峰值电流以控制主开关。
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7.发明授权Programmable electro-magnetic-interference (EMI) reduction with enhanced noise immunity and process tolerance 有权可编程电磁干扰（EMI）降低，增强抗噪声和工艺容差公开(公告)号：US08188798B1
公开(公告)日：2012-05-29
申请号：US12948896
申请日：2010-11-18
申请人： Chi Tak (Gerry) Leung , Chik Wai (David) Ng , Hing Kit Kwan , Wai Kit (Victor) So , Po Wah (Patrick) Chang , Wing Cheong Mak , Kwok Kuen (David) Kwong
发明人： Chi Tak (Gerry) Leung , Chik Wai (David) Ng , Hing Kit Kwan , Wai Kit (Victor) So , Po Wah (Patrick) Chang , Wing Cheong Mak , Kwok Kuen (David) Kwong
CPC分类号： H03L7/08
摘要： A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.
摘要翻译： 频率抖动电路通过扩展时钟的频谱来减少引起电磁干扰（EMI）的辐射。 该时钟是将数字计数值驱动到数模转换器（DAC）的计数器。 DAC输出宽电压摆幅的锯齿波。 减法器缩小电压摆幅，产生用作上限电压的减小摆动锯齿波。 当电流泵对电容器充电和放电超过电压限制时，比较器触发设置复位锁存器来切换时钟。 由于上限电压是来自减法器的减少的锯齿波，所以对电容器充电的时间量变化，使时钟的周期抖动。 可以通过对减法器中的反馈电阻进行编程来调整抖动度。 减法器可降低抖动对DAC误差的灵敏度，从而实现廉价，精度更低的DAC。
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8.发明授权公开(公告)号：US07999512B2
公开(公告)日：2011-08-16
申请号：US12336514
申请日：2008-12-16
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译： 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。
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9.发明授权公开(公告)号：US08643337B2
公开(公告)日：2014-02-04
申请号：US13179107
申请日：2011-07-08
IPC分类号： H02J7/00
CPC分类号： H02J7/0031
摘要： A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.
摘要翻译： 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点，以关闭功率晶体管，从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压，并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关，其将升压电压的时钟驱动到栅极耦合晶体管的栅极，以关断功率晶体管。
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10.发明授权Slew-rate-enhanced error amp with adaptive transconductance and single dominant pole shared by main and auxiliary amps 有权具有自适应跨导的转换率增益误差放大器和主和辅助放大器共享的单个主导极公开(公告)号：US07795976B2
公开(公告)日：2010-09-14
申请号：US12345862
申请日：2008-12-30
申请人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
发明人： Yat To William Wong , Chik Wai David Ng , Ho Ming Karen Wan , Kam Chuen Wan , Kwok Kuen David Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F3/3023 , H03F3/45475 , H03F2203/45248 , H03F2203/45646 , H03F2203/45652 , H03F2203/45678
摘要： An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers.
摘要翻译： 误差放大器可用于控制功率调节晶体管。 误差放大器具有主放大器，上拉辅助放大器和全部驱动输出的下拉辅助放大器。 输出上的补偿电容为所有放大器设置单个主极，从而提高稳定性。 当差分输入具有大于有意偏移的绝对电压差时，来自辅助放大器的增加的转换电流提供高转换速率。 通过调整辅助放大器的一个支路中的p沟道至n沟道晶体管比，将有意的偏移引入辅助放大器。 主放大器中的源极退化电阻通过连接接收差分输入的两个差分晶体管的源极减小了供电余量并增加了线性度。 串联晶体管增加了增益和输出阻抗。 在放大器中没有使用正反馈的情况下，可靠性提高。
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