公开(公告)号：US20070096774A1

公开(公告)日：2007-05-03

申请号：US11261880

申请日：2005-10-28

申请人： Chia-hao Yang ,  Tze-hsiang Chao

发明人： Chia-hao Yang ,  Tze-hsiang Chao

IPC分类号： G06F1/08

CPC分类号： G06F1/08

摘要： A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

摘要翻译： 描述了在集成电路领域中应用的时钟切换系统。 相位插值器将输入时钟信号转换成时钟A和时钟B，其间具有相位差，并发送时钟A和时钟B。 连接到相位插值器的开关指令单元接收作为触发信号的时钟A或时钟B，用于触发开关指令单元，以在输出开关信号位于上升沿或下降沿时将输入切换信号变换为输出切换信号 一个下降的边缘。 连接到相位插值器和开关指令单元的选择装置根据来自开关指令单元的输出切换信号选择clock_A或clock_B，以输出由clock_A和clock_B组成的时钟切换信号。

公开(公告)号：US20070090862A1

公开(公告)日：2007-04-26

申请号：US11320254

申请日：2005-12-27

申请人： Tze-hsiang Chao ,  Chia-hao Yang ,  Chia-jung Liu

发明人： Tze-hsiang Chao ,  Chia-hao Yang ,  Chia-jung Liu

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812

摘要： An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signals and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signals. The controller controls the coarse calibration unit and the first fine calibration unit to align the feedback signal to the reference signal according to the indicating signal generated from the phase detector. The rotating detector rapidly tunes the phase difference between the feedback signal and the reference signal by adding a number of time delays to the feedback signal when the feedback signal and the reference signal are miss-aligned.

摘要翻译： 描述了一种用于电子设备中的时钟源同步的混合相位和时域的双环控制和调谐时钟相位对准的装置和方法。 粗略校准单元产生多个输出信号，输出信号之间具有多个固定相间隔。 固定相位间隔中的至少一个等于完成360度，其除以输出信号的数量以覆盖完整360度的相位范围。 连接到粗校准单元的第一精细校准单元通过耦合可编程延迟电路来延迟从粗校准单元生成的输出信号，以将反馈信号的相位调整到参考信号的相位。 连接到第一精细校准单元的相位检测器用于检测参考和反馈信号之间的相位差，并输出与参考和反馈信号之间的相位差对应的指示信号。 控制器控制粗略校准单元和第一精细校准单元，以根据从相位检测器产生的指示信号将反馈信号与参考信号对准。 当反馈信号和参考信号错过对准时，旋转检测器通过向反馈信号添加多个时间延迟来快速调谐反馈信号和参考信号之间的相位差。

公开(公告)号：US08971378B2

公开(公告)日：2015-03-03

申请号：US13308559

申请日：2011-12-01

申请人： Li-Chun Tu ,  Chia-Hao Yang ,  Tsung-Huang Chen

发明人： Li-Chun Tu ,  Chia-Hao Yang ,  Tsung-Huang Chen

IPC分类号： H04B1/00 ,  H04B1/40

CPC分类号： H04B1/40

摘要： A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.

摘要翻译： 提供一种包括集成处理电路和第一存储器的无线通信装置。 集成处理电路包括能够处理无线通信信号的处理单元和能够执行射频（RF）信号和基带信号之间的转换的射频（RF）单元，其中无线通信信号是 RF信号和基带信号。 第一存储器耦合到集成处理电路。 第一存储器能够存储由处理单元使用的数据，其中集成处理电路和第一存储器封装在单个半导体封装中。

公开(公告)号：US07411429B2

公开(公告)日：2008-08-12

申请号：US11261880

申请日：2005-10-28

申请人： Chia-hao Yang ,  Tze-hsiang Chao

发明人： Chia-hao Yang ,  Tze-hsiang Chao

IPC分类号： G06F1/08

CPC分类号： G06F1/08

摘要： A system for clock-switching applied in the field of integrated circuits is described. A phase interpolator converts an input clock signal into a clock_A and a clock_B having a phase difference therebetween and transmitting the clock_A and the clock_B. A switch command unit connected to the phase interpolator receives either the clock_A or the clock_B serving as a triggering signal for triggering the switch command unit to transform an input switching signal into an output switching signal when the output switching signal is located in either a rising or a falling edge. A selecting device connected to the phase interpolator and the switch command unit, selects either clock_A or clock_B according to the output switching signal from the switch command unit to output a clock-switching signal composed of clock_A and clock_B.

摘要翻译： 描述了在集成电路领域中应用的时钟切换系统。 相位插值器将输入时钟信号转换成时钟A和时钟B，其间具有相位差，并发送时钟A和时钟B。 连接到相位插值器的开关指令单元接收作为触发信号的时钟A或时钟B，用于触发开关指令单元，以在输出开关信号位于上升沿或下降沿时将输入切换信号变换为输出切换信号 一个下降的边缘。 连接到相位插值器和开关指令单元的选择装置根据来自开关指令单元的输出切换信号选择clock_A或clock_B，以输出由clock_A和clock_B组成的时钟切换信号。

公开(公告)号：US07603095B2

公开(公告)日：2009-10-13

申请号：US11356931

申请日：2006-02-17

申请人： Chia-hao Yang ,  Chia-jung Liu

发明人： Chia-hao Yang ,  Chia-jung Liu

IPC分类号： H04B1/06

CPC分类号： H03L7/07 ,  H03L7/0812

摘要： The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into. The present invention also provides a method for reducing heavy switching between two coarse intervals. It is obvious that the probability of the heavy switching occurring will be efficiently decreased by the way of hysteretic switching of the present invention. Furthermore, the mismatch and noises due to the heavy switching between the coarse intervals can be effectively diminished.

摘要翻译： 本发明提供了一种用于有效地减少两个相邻粗略间隔之间的重切换的滞后切换的方式。 本发明可以配置多个精细间隔以覆盖大于一个粗略间隔的长度的范围。 每个粗略间隔包括超过一侧的粗略间隔的边界的一些额外的精细间隔。 重型切换将被推迟，直到超级间隔用尽。 同时，精密校准单元记录使用的精细间隔的数量。 如果发生重切换，则在精细校准单元中将记录超边界值以确定另一粗略间隔中的初始精细间隔。 应当注意，外边界值可以是对应于参考信号漂移的前向粗略间隔或后向粗略间隔的正或负值。 本发明还提供一种用于减少两个粗间隔之间的重切换的方法。 显然，通过本发明的滞后切换的方式，可以有效地降低发生重切换的可能性。 此外，可以有效地减少由于粗间隔之间的重切换引起的失配和噪声。

公开(公告)号：US20070197181A1

公开(公告)日：2007-08-23

申请号：US11356931

申请日：2006-02-17

申请人： Chia-hao Yang ,  Chia-jung Liu

发明人： Chia-hao Yang ,  Chia-jung Liu

IPC分类号： H04B1/06

CPC分类号： H03L7/07 ,  H03L7/0812

摘要： The present invention provides a way of hysteretic switching for efficiently reducing the heavy switching between two adjacent coarse intervals. The present invention disposes a number of fine intervals to cover a range which is larger than the length of one coarse interval. Each coarse interval comprises some extra fine intervals which are exceeded the boundary of the coarse intervals in one side. The heavy switching will be postponed until the extra fine intervals are used up. In the meantime, the fine calibration unit records the number of extra fine interval which be used. An extra-boundary value will be recorded in the fine calibration unit for determining an initial fine interval in another coarse interval if the heavy switching occurs. It should be noted that the extra-boundary value could be a positive or minus value corresponding to which a forward coarse interval or a backward coarse interval the reference signal drifts into. The present invention also provides a method for reducing heavy switching between two coarse intervals. It is obvious that the probability of the heavy switching occurring will be efficiently decreased by the way of hysteretic switching of the present invention. Furthermore, the mismatch and noises due to the heavy switching between the coarse intervals can be effectively diminished.

摘要翻译： 本发明提供了一种用于有效地减少两个相邻粗略间隔之间的重切换的滞后切换的方式。 本发明可以配置多个精细间隔以覆盖大于一个粗略间隔的长度的范围。 每个粗略间隔包括超过一侧的粗略间隔的边界的一些额外的精细间隔。 重型切换将被推迟，直到超级间隔用尽。 同时，精密校准单元记录使用的精细间隔的数量。 如果发生重切换，则在精细校准单元中将记录超边界值以确定另一粗略间隔中的初始精细间隔。 应当注意，外边界值可以是对应于参考信号漂移的前向粗略间隔或后向粗略间隔的正或负值。 本发明还提供一种用于减少两个粗间隔之间的重切换的方法。 显然，通过本发明的滞后切换的方式，可以有效地降低发生重切换的可能性。 此外，可以有效地减少由于粗间隔之间的重切换引起的失配和噪声。

公开(公告)号：US20120207191A1

公开(公告)日：2012-08-16

申请号：US13308559

申请日：2011-12-01

申请人： Li-Chun Tu ,  Chia-Hao Yang ,  Tsung-Huang Chen

发明人： Li-Chun Tu ,  Chia-Hao Yang ,  Tsung-Huang Chen

IPC分类号： H04L27/00 ,  H04B1/713 ,  H04B17/00

CPC分类号： H04B1/40

摘要： A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.

摘要翻译： 提供一种包括集成处理电路和第一存储器的无线通信装置。 集成处理电路包括能够处理无线通信信号的处理单元和能够执行射频（RF）信号和基带信号之间的转换的射频（RF）单元，其中无线通信信号是 RF信号和基带信号。 第一存储器耦合到集成处理电路。 第一存储器能够存储由处理单元使用的数据，其中集成处理电路和第一存储器封装在单个半导体封装中。

公开(公告)号：US20100078865A1

公开(公告)日：2010-04-01

申请号：US12323581

申请日：2008-11-26

申请人： Yung Shuen PAN ,  Chia-Hao YANG

发明人： Yung Shuen PAN ,  Chia-Hao YANG

IPC分类号： H01L21/683

CPC分类号： H01L21/68721 ,  H01L21/68728

摘要： The present invention discloses a sheet clamping apparatus for a reticle, a wafer, a glass substrate, a LCD panel et al. The apparatus comprises a pair of brackets, each bracket having at least one cam groove thereon for defining a movement route by two opposing sides of the cam groove, and one end of each bracket being joined with a connecting frame. One end of a clamping arm is joined with each cam groove, and the other end of the clamping arm is clamping the sheet (ex: a reticle, a wafer, a glass substrate, a LCD panel et al.). The characteristic of the sheet clamping apparatus is that: on the other end of each clamping arm is formed with a clamping head with recess, and at least a pair of rollers are disposed on the recess of clamping head for stably clamping the reticle or a semiconductor component stored in the pod.

摘要翻译： 本发明公开了一种用于掩模版，晶片，玻璃基板，LCD面板等的片材夹紧装置。 该装置包括一对支架，每个支架在其上具有至少一个凸轮槽，用于通过凸轮槽的两个相对侧限定运动路线，并且每个支架的一端与连接框架连接。 夹持臂的一端与每个凸轮槽接合，并且夹紧臂的另一端夹紧片材（例如，掩模版，晶片，玻璃基板，LCD面板等）。 夹紧装置的特征在于：每个夹紧臂的另一端形成有具有凹槽的夹紧头，并且至少一对辊设置在夹紧头的凹部上，用于稳定地夹紧掩模版或半导体 组件存储在pod中。

公开(公告)号：US07202716B1

公开(公告)日：2007-04-10

申请号：US11320254

申请日：2005-12-27

申请人： Tze-hsiang Chao ,  Chia-hao Yang ,  Chia-jung Liu

发明人： Tze-hsiang Chao ,  Chia-hao Yang ,  Chia-jung Liu

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812

摘要： An apparatus and a method of controlling and tuning clock phase alignment with a dual loop of a hybrid phase and time domain for clock source synchronization in electronic devices are described. The coarse calibration unit generates a plurality of output signals, the output signals having a plurality of fixed phase intervals therebetween. At least one of the fixed phase intervals is equal to complete 360 degrees which are divided by the number of the output signals to cover the phase range of complete 360 degrees. The first fine calibration unit connected to the coarse calibration unit delays the output signals generated from the coarse calibration unit by coupling a programmable delay circuit to adjust the phase of a feedback signal toward the phase of a reference signal. The phase detector connected to the first fine calibration unit is used to detect a phase difference between the reference and the feedback signals and outputting an indicating signal corresponding to the phase difference between the reference and the feedback signals. The controller controls the coarse calibration unit and the first fine calibration unit to align the feedback signal to the reference signal according to the indicating signal generated from the phase detector. The rotating detector rapidly tunes the phase difference between the feedback signal and the reference signal by adding a number of time delays to the feedback signal when the feedback signal and the reference signal are miss-aligned.

摘要翻译： 描述了一种用于电子设备中的时钟源同步的混合相位和时域的双环控制和调谐时钟相位对准的装置和方法。 粗略校准单元产生多个输出信号，输出信号之间具有多个固定相间隔。 固定相位间隔中的至少一个等于完成360度，其除以输出信号的数量以覆盖完整360度的相位范围。 连接到粗校准单元的第一精细校准单元通过耦合可编程延迟电路来延迟从粗校准单元生成的输出信号，以将反馈信号的相位调整到参考信号的相位。 连接到第一精细校准单元的相位检测器用于检测参考和反馈信号之间的相位差，并输出与参考和反馈信号之间的相位差对应的指示信号。 控制器控制粗略校准单元和第一精细校准单元，以根据从相位检测器产生的指示信号将反馈信号与参考信号对准。 当反馈信号和参考信号错过对准时，旋转检测器通过向反馈信号添加多个时间延迟来快速调谐反馈信号和参考信号之间的相位差。