摘要:
A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory.
摘要:
A double data rate pseudo SRAM (DDR PSRAM) is provided. The DDR PSRAM includes a data receiver, a memory and an address decoder. The data receiver receives a first single data rate data from a controller via a common bus according to a clock, and receives a double data rate data from the controller via the common bus according to a data strobe signal from the controller. The address decoder decodes the first single data rate data to obtain an address of the memory. The data receiver stores the double data rate data into the address of the memory.
摘要:
A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.
摘要:
A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal.
摘要:
A controller for a DDR PSRAM is provided. The controller includes a single rate processing unit, a double rate processing unit and a selector. The signal rate processing unit obtains a single data rate data according to a first data and a first clock. The double rate processing unit obtains a double data rate data according to a second data and a second clock that is two times the frequency of the first clock. The selector selectively provides any of the single data rate data and the double data rate data to the DDR PSRAM via a common bus according to a control signal.
摘要:
A wireless communication device including an integrated processing circuit and a first memory is provided. The integrated processing circuit includes a processing unit capable of processing a wireless communication signal and a radio frequency (RF) unit capable of performing a conversion between a radio frequency (RF) signal and a baseband signal, wherein the wireless communication signal is one of the RF signal and the baseband signal. The first memory is coupled to the integrated processing circuit. The first memory is capable of storing data used by the processing unit, wherein the integrated processing circuit and the first memory are packaged in a single semiconductor package.