公开(公告)号：US08549277B2

公开(公告)日：2013-10-01

申请号：US12884208

申请日：2010-09-17

Applicant: Chiang-Chung Tang

Inventor： Chiang-Chung Tang

IPC: G06F9/00

CPC classification number: G06F11/1433

Abstract: A server system includes a BMC, a BIOS chip, an IPMI and a diplexer. The BMC includes a first chip-selecting signal output terminal, a second chip-selecting signal output terminal, a first updating output terminal and a controlling input terminal. The BIOS chip includes a second chip-selecting signal input terminal and an updating input terminal. The IPMI has a controlling output terminal. The diplexer includes a first input terminal and an updating output terminal. The first input terminal of the diplexer is electrically coupled to the first updating output terminal of BMC. The updating output terminal of the diplexer is electrically coupled to the updating input terminal of the BIOS chip. The controlling output terminal of the IPMI is electrically coupled to the controlling input terminal of the BMC. The second chip-selecting signal input terminal of the BIOS chip is electrically coupled to the second chip-selecting signal output terminal of the BMC.

Abstract translation: 服务器系统包括BMC，BIOS芯片，IPMI和双工器。 BMC包括第一芯片选择信号输出端子，第二芯片选择信号输出端子，第一更新输出端子和控制输入端子。 BIOS芯片包括第二芯片选择信号输入端和更新输入端。 IPMI具有控制输出端子。 双工器包括第一输入端和更新输出端。 双工器的第一输入端子电连接到BMC的第一更新输出端子。 双工器的更新输出端子电耦合到BIOS芯片的更新输入端子。 IPMI的控制输出端子电连接到BMC的控制输入端子。 BIOS芯片的第二芯片选择信号输入端子电耦合到BMC的第二芯片选择信号输出端子。

公开(公告)号：US08250264B2

公开(公告)日：2012-08-21

申请号：US12641590

申请日：2009-12-18

Applicant: Chiang-Chung Tang

Inventor： Chiang-Chung Tang

IPC: G06F12/16 ,  H03M7/30

CPC classification number: G06F11/1441 ,  G06F11/1456 ,  H03M7/4006

Abstract: A method for performing data backup using a storage device starts a backup battery when an electronic device is powered off, reads data from a memory of the electronic device by a system on chip (SoC) of the storage device, and writes the data into a field programmable gate array (FPGA) of the storage device. The method further encodes the data by the FPGA, and stores the encoded data into a flash memory of the storage device.

Abstract translation: 使用存储设备执行数据备份的方法在电子设备断电时启动备用电池，通过存储设备的片上系统（SoC）从电子设备的存储器读取数据，并将数据写入 存储设备的现场可编程门阵列（FPGA）。 该方法通过FPGA对数据进行编码，并将编码的数据存储到存储设备的闪速存储器中。

公开(公告)号：US20120144180A1

公开(公告)日：2012-06-07

申请号：US13172860

申请日：2011-06-30

Applicant: CHIANG-CHUNG TANG

Inventor： CHIANG-CHUNG TANG

IPC: G06F15/177

CPC classification number: G06F9/50 ,  G06F13/4282 ,  G06F13/4286

Abstract: A baseboard management controller (BMC) connects with a COM serial port. The BMC includes an input queue and an output queue. If a basic input output system (BIOS) of the BMC has been initialized, the COM serial port is used by the BIOS. When a processor of the BMC sends a control command to a sharing system of the BMC, the input queue and the output queue are converted to time division multiplex (TDM) queues. The COM serial port may be used by the BIOS or by the BMC according to an ID flag of each element of the TDM queues.

Abstract translation: 基板管理控制器（BMC）与COM串行端口连接。 BMC包括输入队列和输出队列。 如果BMC的基本输入输出系统（BIOS）已经初始化，则COM使用COM串行端口。 当BMC的处理器向BMC的共享系统发送控制命令时，将输入队列和输出队列转换为时分复用（TDM）队列。 COM串行端口可以由BIOS或BMC根据TDM队列的每个元素的ID标志使用。

公开(公告)号：US07971114B2

公开(公告)日：2011-06-28

申请号：US12504808

申请日：2009-07-17

Applicant: Mo-Ying Tong ,  Xue-Wen Hong ,  Chiang-Chung Tang

Inventor： Mo-Ying Tong ,  Xue-Wen Hong ,  Chiang-Chung Tang

IPC: G11C29/00

CPC classification number: G11C29/10

Abstract: A method for testing a random-access memory (RAM) includes six tests. The first test is performed by performing a write and read test to storage locations of the RAM. The second test is performed by testing walking 1's across each data bus of the RAM. The third test is performed by testing walking 0's across the data bus of the RAM. The fourth test is performed by testing walking 1's across each address bus of the RAM. The fifth test is performed by testing walking 0's across the address bus bit of the RAM. The sixth test is performed by performing a write and read test to random blocks in the storage locations of the RAM.

Abstract translation: 用于测试随机存取存储器（RAM）的方法包括六个测试。 通过对RAM的存储位置执行写入和读取测试来执行第一个测试。 第二个测试是通过测试RAM的每个数据总线上的步行1来执行的。 第三个测试是通过在RAM的数据总线上测试步数0来执行的。 第四个测试是通过测试RAM的每个地址总线上的步行1来执行的。 第五个测试是通过在RAM的地址总线位上测试步行0来执行的。 通过对RAM的存储位置中的随机块执行写入和读取测试来执行第六测试。

公开(公告)号：US20110029151A1

公开(公告)日：2011-02-03

申请号：US12826709

申请日：2010-06-30

Applicant: CHIANG-CHUNG TANG ,  WEI LIAO

Inventor： CHIANG-CHUNG TANG ,  WEI LIAO

IPC: G05D23/19 ,  G05D13/00

CPC classification number: G05D23/1917

Abstract: In a temperature adjustment system and method for a storage system, a corresponding relationship between data transfer rates of the storage system and rotational speeds of electric fans coupled to the storage system is established. Real-time data transfer rates of the storage system are measured. If there is a continuous increase or decrease in data transfer rates of the storage system, a rotational speed of the electric fans is determined according to the real-time data transfer rates and the corresponding relationship. The electric fans are controlled to run at the determined rotational speed.

Abstract translation: 在用于存储系统的温度调节系统和方法中，建立了存储系统的数据传送速率与耦合到存储系统的电风扇的转速之间的对应关系。 测量存储系统的实时数据传输速率。 如果存储系统的数据传输速率持续增加或减少，则根据实时数据传输速率和相应的关系确定电风扇的转速。 控制电风扇以确定的转速运行。

公开(公告)号：US20110016262A1

公开(公告)日：2011-01-20

申请号：US12641590

申请日：2009-12-18

Applicant: CHIANG-CHUNG TANG

Inventor： CHIANG-CHUNG TANG

IPC: G06F12/16

CPC classification number: G06F11/1441 ,  G06F11/1456 ,  H03M7/4006

Abstract: A method for performing data backup using a storage device starts a backup battery when an electronic device is powered off, reads data from a memory of the electronic device by a system on chip (SoC) of the storage device, and writes the data into a field programmable gate array (FPGA) of the storage device. The method further encodes the data by the FPGA, and stores the encoded data into a flash memory of the storage device.

Abstract translation: 使用存储设备执行数据备份的方法在电子设备断电时启动备用电池，通过存储设备的片上系统（SoC）从电子设备的存储器读取数据，并将数据写入 存储设备的现场可编程门阵列（FPGA）。 该方法通过FPGA对数据进行编码，并将编码的数据存储到存储设备的闪速存储器中。

公开(公告)号：US07840843B2

公开(公告)日：2010-11-23

申请号：US12198040

申请日：2008-08-25

Applicant: Mo-Ying Tong ,  Hua Dong ,  Xue-Wen Hong ,  Chiang-Chung Tang ,  Hong-Bo Zhao

Inventor： Mo-Ying Tong ,  Hua Dong ,  Xue-Wen Hong ,  Chiang-Chung Tang ,  Hong-Bo Zhao

IPC: G06F11/00

CPC classification number: G06F11/2294

Abstract: A testing system for an embedded system is provided. The testing system includes a plurality of devices and one or more host computers. Each device, which includes the embedded system to be tested, is connected to the host computer via a network based on the network file system protocol. The host computers are further connected with a control server, and each of the host computers comprises a root file system. The control server is configured for providing an interface for a user to set test parameters, controlling each of the host computers to invoke a test program, thereby testing the embedded system according to the test parameters, and receiving test results of the embedded system from the host computer. A related testing method is also provided.

Abstract translation: 提供了嵌入式系统的测试系统。 测试系统包括多个设备和一个或多个主机计算机。 每个设备（包括待测试的嵌入式系统）通过基于网络文件系统协议的网络连接到主机。 主计算机进一步与控制服务器连接，并且每个主计算机包括根文件系统。 控制服务器被配置为提供用于用户设置测试参数的接口，控制每个主计算机来调用测试程序，从而根据测试参数测试嵌入式系统，并从嵌入式系统的测试结果接收测试结果 主机。 还提供了相关的测试方法。

公开(公告)号：US20100211835A1

公开(公告)日：2010-08-19

申请号：US12504808

申请日：2009-07-17

Applicant: MO-YING TONG ,  XUE-WEN HONG ,  CHIANG-CHUNG TANG

Inventor： MO-YING TONG ,  XUE-WEN HONG ,  CHIANG-CHUNG TANG

IPC: G11C29/10 ,  G06F11/263

CPC classification number: G11C29/10

Abstract: A method for testing a random-access memory (RAM) includes six tests. The first test is performed by performing a write and read test to storage locations of the RAM. The second test is performed by testing walking 1's across each data bus of the RAM. The third test is performed by testing walking 0's across the data bus of the RAM. The fourth test is performed by testing walking 1's across each address bus of the RAM. The fifth test is performed by testing walking 0's across the address bus bit of the RAM. The sixth test is performed by performing a write and read test to random blocks in the storage locations of the RAM.

Abstract translation: 用于测试随机存取存储器（RAM）的方法包括六个测试。 通过对RAM的存储位置执行写入和读取测试来执行第一个测试。 第二个测试是通过测试RAM的每个数据总线上的步行1来执行的。 第三个测试是通过在RAM的数据总线上测试步行0来执行的。 第四个测试是通过测试RAM的每个地址总线上的步行1来执行的。 第五个测试是通过在RAM的地址总线位上测试步行0来执行的。 通过对RAM的存储位置中的随机块执行写入和读取测试来执行第六测试。

公开(公告)号：US20090132857A1

公开(公告)日：2009-05-21

申请号：US12198040

申请日：2008-08-25

Applicant: MO-YING TONG ,  HUA DONG ,  XUE-WEN HONG ,  CHIANG-CHUNG TANG ,  HONG-BO ZHAO

Inventor： MO-YING TONG ,  HUA DONG ,  XUE-WEN HONG ,  CHIANG-CHUNG TANG ,  HONG-BO ZHAO

IPC: G06F11/00

CPC classification number: G06F11/2294

Abstract: A testing system for an embedded system is provided. The testing system includes a plurality of devices and one or more host computers. Each device, which includes the embedded system to be tested, is connected to the host computer via a network based on the network file system protocol. The host computers are further connected with a control server, and each of the host computers comprises a root file system. The control server is configured for providing an interface for a user to set test parameters, controlling each of the host computers to invoke a test program, thereby testing the embedded system according to the test parameters, and receiving test results of the embedded system from the host computer. A related testing method is also provided.

Abstract translation: 提供了嵌入式系统的测试系统。 测试系统包括多个设备和一个或多个主机计算机。 每个设备（包括待测试的嵌入式系统）通过基于网络文件系统协议的网络连接到主机。 主计算机进一步与控制服务器连接，并且每个主计算机包括根文件系统。 控制服务器被配置为提供用于用户设置测试参数的接口，控制每个主计算机来调用测试程序，从而根据测试参数测试嵌入式系统，并从嵌入式系统的测试结果接收测试结果 主机。 还提供了相关的测试方法。

公开(公告)号：US08838870B2

公开(公告)日：2014-09-16

申请号：US13172860

申请日：2011-06-30

Applicant: Chiang-Chung Tang

Inventor： Chiang-Chung Tang

IPC: G06F13/42 ,  G06F9/50

CPC classification number: G06F9/50 ,  G06F13/4282 ,  G06F13/4286

Abstract: A baseboard management controller (BMC) connects with a COM serial port. The BMC includes an input queue and an output queue. If a basic input output system (BIOS) of the BMC has been initialized, the COM serial port is used by the BIOS. When a processor of the BMC sends a control command to a sharing system of the BMC, the input queue and the output queue are converted to time division multiplex (TDM) queues. The COM serial port may be used by the BIOS or by the BMC according to an ID flag of each element of the TDM queues.

Abstract translation: 基板管理控制器（BMC）与COM串行端口连接。 BMC包括输入队列和输出队列。 如果BMC的基本输入输出系统（BIOS）已经初始化，则COM使用COM串行端口。 当BMC的处理器向BMC的共享系统发送控制命令时，将输入队列和输出队列转换为时分复用（TDM）队列。 COM串行端口可以由BIOS或BMC根据TDM队列的每个元素的ID标志使用。