公开(公告)号：US20120243346A1

公开(公告)日：2012-09-27

申请号：US13488937

申请日：2012-06-05

Applicant: Yu-Sheng CHEN ,  Heng-Yuan LEE ,  Yen-Ya HSU ,  Pang-Shiu CHEN ,  Ching-Chih HSU ,  Frederick T. CHEN

Inventor： Yu-Sheng CHEN ,  Heng-Yuan LEE ,  Yen-Ya HSU ,  Pang-Shiu CHEN ,  Ching-Chih HSU ,  Frederick T. CHEN

IPC: G11C7/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

Abstract: A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

Abstract translation: 一种用于至少一个存储单元的控制方法。 存储单元包括晶体管和电阻器。 电阻器在第一节点和第二节点之间串联连接到晶体管。 在编程模式下，存储单元被编程。 当确定存储器单元已被成功编程时，存储器单元的阻抗处于第一状态。 当确定存储器单元未被成功编程时，执行特定动作来重置存储器单元。 在步骤重置存储单元之后，存储单元的阻抗处于第二状态。 第二状态下的存储单元的阻抗高于第一状态下的存储单元的阻抗。

公开(公告)号：US08223528B2

公开(公告)日：2012-07-17

申请号：US12649286

申请日：2009-12-29

Applicant: Yu-Sheng Chen ,  Heng-Yuan Lee ,  Yen-Ya Hsu ,  Pang-Shiu Chen ,  Ching-Chih Hsu

Inventor： Yu-Sheng Chen ,  Heng-Yuan Lee ,  Yen-Ya Hsu ,  Pang-Shiu Chen ,  Ching-Chih Hsu

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

Abstract: A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor between a first node and a second node. In a programming mode, the memory cell is programmed. The step of programming the memory cell includes providing a first controlling voltage to a gate of the transistor, providing a first setting voltage to the first node, and providing a second setting voltage to the second node. When it is determined that the memory cell has been successfully programmed, a specific action is executed.

Abstract translation: 公开了至少一个存储单元的控制方法。 存储单元包括晶体管和电阻器。 电阻器连接到第一节点和第二节点之间的晶体管。 在编程模式下，存储单元被编程。 编程存储单元的步骤包括向晶体管的栅极提供第一控制电压，向第一节点提供第一设定电压，并向第二节点提供第二设定电压。 当确定存储器单元已被成功编程时，执行特定动作。

公开(公告)号：US08817521B2

公开(公告)日：2014-08-26

申请号：US13488937

申请日：2012-06-05

Applicant: Yu-Sheng Chen ,  Heng-Yuan Lee ,  Yen-Ya Hsu ,  Pang-Shiu Chen ,  Ching-Chih Hsu ,  Frederick T. Chen

Inventor： Yu-Sheng Chen ,  Heng-Yuan Lee ,  Yen-Ya Hsu ,  Pang-Shiu Chen ,  Ching-Chih Hsu ,  Frederick T. Chen

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

Abstract: A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

Abstract translation: 公开了至少一个存储单元的控制方法。 存储单元包括晶体管和电阻器。 电阻器在第一节点和第二节点之间串联连接到晶体管。 在编程模式下，存储单元被编程。 当确定存储器单元已被成功编程时，存储器单元的阻抗处于第一状态。 当确定存储器单元未成功编程时，执行特定动作来重置存储器单元。 在步骤重置存储单元之后，存储单元的阻抗处于第二状态。 第二状态下的存储单元的阻抗高于第一状态下的存储单元的阻抗。

公开(公告)号：US20110122714A1

公开(公告)日：2011-05-26

申请号：US12649286

申请日：2009-12-29

Applicant: Yu-Sheng CHEN ,  Heng-Yuan LEE ,  Yen-Ya HSU ,  Pang-Shiu CHEN ,  Ching-Chih HSU

Inventor： Yu-Sheng CHEN ,  Heng-Yuan LEE ,  Yen-Ya HSU ,  Pang-Shiu CHEN ,  Ching-Chih HSU

IPC: G11C7/00

CPC classification number: G11C13/0069 ,  G11C13/0064 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2213/79

Abstract: A control method for at least one memory cell is disclosed. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor between a first node and a second node. In a programming mode, the memory cell is programmed. The step of programming the memory cell includes providing a first controlling voltage to a gate of the transistor, providing a first setting voltage to the first node, and providing a second setting voltage to the second node. When it is determined that the memory cell has been successfully programmed, a specific action is executed.

Abstract translation: 公开了至少一个存储单元的控制方法。 存储单元包括晶体管和电阻器。 电阻器连接到第一节点和第二节点之间的晶体管。 在编程模式下，存储单元被编程。 编程存储单元的步骤包括向晶体管的栅极提供第一控制电压，向第一节点提供第一设定电压，并向第二节点提供第二设定电压。 当确定存储器单元已被成功编程时，执行特定动作。