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公开(公告)号：US20050117421A1
公开(公告)日：2005-06-02
申请号：US10711982
申请日：2004-10-18
申请人： Juergen Pille , Rolf Sautter , Christian Schweizer , Klaus Thumm
发明人： Juergen Pille , Rolf Sautter , Christian Schweizer , Klaus Thumm
CPC分类号： G11C7/12 , G11C7/22 , G11C2207/2227
摘要： The present invention relates to computer hardware and in particular to power management of high frequency storage designs, which are able to implement differential write or read access in a dynamic hardware arrangement of storage cells having some inner segmentation. More particularly, the present invention relates to a method and respective system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is realized by determining whether an access operation following a current access operation is a read or write access, and performing a precharge of the bitlines of the array only when a read operation follows the current access operation. A conventional precharge control signal (20) is combined with an external control signal (22) indicating if the next cycle is a read cycle. The combination of the two signals can be used, for example, as input to a simple AND gate to generate an effective precharge signal (24). The effective precharge signal permits precharging of bitlines only when those bitlines are used for read access in a respective next cycle.
摘要翻译： 本发明涉及计算机硬件，特别涉及高频存储设计的电源管理，其能够在具有一些内部分段的存储单元的动态硬件布置中实现差分写入或读取访问。 更具体地说，本发明涉及访问由位线预充电电路操作的动态硬件存储块内的存储器单元的方法和各自的系统，其中通过激活补充位线执行差分读/写访问操作。 通过确定当前访问操作之后的访问操作是读取还是写入访问，并且仅当读取操作遵循当前访问操作时才执行阵列的位线的预充电来实现功耗的降低。 传统的预充电控制信号（20）与外部控制信号（22）组合，指示下一个周期是否为读周期。 两个信号的组合可以用作例如简单与门的输入，以产生有效的预充电信号（24）。 只有当这些位线用于在相应的下一周期中的读取访问时，有效的预充电信号才允许位线预充电。
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公开(公告)号：US20060085778A1
公开(公告)日：2006-04-20
申请号：US11163449
申请日：2005-10-19
CPC分类号： G06F17/5068
摘要： The present invention relates to a method for designing a hierarchical, multi-layer integrated circuit (IC) chip design in which a first stage design at a lower level of the hierarchical design provides details of circuit features that occupy areas of the design, and in a higher level stage of the design process corresponding to a higher level of the hierarchy, those details are used to determine free areas in the lower level design that are not yet occupied by circuit features, and allowing further processing of those free areas during the higher level design stage. For example, this may include identifying free tracks within a basic power grid layer and implementing additional power wiring within that power grid layer without having to redo the lower level design.
摘要翻译： 本发明涉及一种用于设计分级多层集成电路（IC）芯片设计的方法，其中在分级设计的较低级别的第一级设计提供占据设计区域的电路特征的细节，以及 设计过程的较高阶段对应于较高级别的层次，这些细节用于确定尚未被电路特征占用的较低级别设计中的自由区域，并允许在较高级别期间对这些空闲区域进行进一步处理 水平设计阶段。 例如，这可以包括识别基本电力网层内的自由轨道，并且在该电力网格层内实现附加电力线路，而不必重做较低级别的设计。
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公开(公告)号：US06977863B2
公开(公告)日：2005-12-20
申请号：US11051594
申请日：2005-02-04
CPC分类号： G11C8/10 , G11C7/1075
摘要： A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.
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公开(公告)号：US07295481B2
公开(公告)日：2007-11-13
申请号：US10711982
申请日：2004-10-18
申请人： Juergen Pille , Rolf Sautter , Christian Schweizer , Klaus Thumm
发明人： Juergen Pille , Rolf Sautter , Christian Schweizer , Klaus Thumm
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C2207/2227
摘要： A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is realized by determining whether a next access operation following a current access operation is a read or write access, and performing a precharge of the bitlines of the array only when a read operation follows the current access operation. A conventional precharge control signal is combined with an external control signal indicating if the next cycle is a read cycle. The combination of the two signals can be used, for example, as input to a simple AND gate to generate an effective precharge signal. The effective precharge signal permits precharging of bitlines only when those bitlines are used for read access in a respective next cycle.
摘要翻译： 一种访问由位线预充电电路操作的动态硬件存储器块内的存储器单元的方法和系统，其中通过激活补充位线执行差分读/写访问操作。 通过确定当前访问操作之后的下一个访问操作是读取还是写入访问，并且仅当读取操作遵循当前访问操作时才执行阵列的位线的预充电来实现功耗的降低。 常规的预充电控制信号与指示下一个周期是否为读周期的外部控制信号组合。 两个信号的组合可以用作例如简单与门的输入以产生有效的预充电信号。 只有当这些位线用于在相应的下一周期中的读取访问时，有效的预充电信号才允许位线预充电。
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公开(公告)号：US20050128845A1
公开(公告)日：2005-06-16
申请号：US11051594
申请日：2005-02-04
CPC分类号： G11C8/10 , G11C7/1075
摘要： A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.
摘要翻译： 一种用于将地址字解码为字线信号的方法和装置。 多个地址线将地址字馈送到多个解码块，每个解码块与由用于产生相应字线信号的地址字形成的地址空间中的特定地址相关联，由此每个解码块连接到多个解码块 的地址线。 省略与由地址字形成的地址空间中的预定地址相关联的至少一个解码块，使得只要在多个地址线上输入预定的地址字，就不会将生成的字线切换到活动状态 。
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公开(公告)号：US06873567B2
公开(公告)日：2005-03-29
申请号：US10636387
申请日：2003-08-07
CPC分类号： G11C8/10 , G11C7/1075
摘要： A method and a device for decoding an address word into word-line signals. A plurality of address lines feed the address word into a plurality of decoding blocks each associated to a particular address in the address space formed by the address word for generating a respective word-line signals, whereby each of the decoding blocks is connected to the plurality of address lines. At least one decoding block associated to a predetermined address in the address space formed by the address word is omitted, so that none of the generated word lines is switched to the active state, whenever the predetermined address word is inputted over the plurality of address lines.
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