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    TRANSCEIVER MODULE AND INTEGRATED CIRCUIT WITH DUAL EYE OPENERS
    1.
    发明申请
    TRANSCEIVER MODULE AND INTEGRATED CIRCUIT WITH DUAL EYE OPENERS 有权
    收发器模块和集成电路与双眼打开器

    公开(公告)号：US20110293285A1

    公开(公告)日：2011-12-01

    申请号：US13205531

    申请日：2011-08-08

    申请人： Lewis B. Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    发明人： Lewis B. Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    IPC分类号： H04B10/00

    CPC分类号： H04B10/40 ,  H04L7/033 ,  H04L25/242

    摘要： A transceiver module having integrated eye diagram opening functionality for reducing jitter is described. The transceiver module may include a transmitter eye opener and a receiver eye opener integrated in a single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modes, bypass features, bit error rate testing, and power down modes.

    摘要翻译： 描述了具有用于减少抖动的综合眼图打开功能的收发器模块。 收发器模块可以包括集成在单个电路中的发射器眼睛开启器和接收器眼睛开启器。 收发器模块还可以包括串行控制和各种其它集成组件。 可以集成在收发器模块上的其他功能包括环回模式，旁路功能，误码率测试和掉电模式。

    TRANSCEIVER MODULE AND INTEGRATED CIRCUIT WITH DUAL EYE OPENERS
    2.
    发明申请
    TRANSCEIVER MODULE AND INTEGRATED CIRCUIT WITH DUAL EYE OPENERS 有权
    收发器模块和集成电路与双眼打开器

    公开(公告)号：US20100111539A1

    公开(公告)日：2010-05-06

    申请号：US12611098

    申请日：2009-11-02

    申请人： Lewis B. Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    发明人： Lewis B. Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    IPC分类号： H04B10/00

    CPC分类号： H04B10/40 ,  H04L7/033 ,  H04L25/242

    摘要： A transceiver module having integrated eye diagram opening functionality for reducing jitter is described. The transceiver module may include a transmitter eye opener and a receiver eye opener integrated in a single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modes, bypass features, bit error rate testing, and power down modes.

    摘要翻译： 描述了具有用于减少抖动的综合眼图打开功能的收发器模块。 收发器模块可以包括集成在单个电路中的发射器眼睛开启器和接收器眼睛开启器。 收发器模块还可以包括串行控制和各种其它集成组件。 可以集成在收发器模块上的其他功能包括环回模式，旁路功能，误码率测试和掉电模式。

    Transceiver module and integrated circuit with dual eye openers
    4.
    发明申请
    Transceiver module and integrated circuit with dual eye openers 有权
    收发模块和集成电路与双眼开启

    公开(公告)号：US20070031153A1

    公开(公告)日：2007-02-08

    申请号：US10420027

    申请日：2003-04-17

    申请人： Lewis Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    发明人： Lewis Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    IPC分类号： H04B10/00

    CPC分类号： H04B10/40 ,  H04L7/033 ,  H04L25/242

    摘要： A transceiver module having integrated eye diagram opening functionality for reducing jitter is described. The transceiver module may include a transmitter eye opener and a receiver eye opener integrated in a single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modes, bypass features, bit error rate testing, and power down modes.

    摘要翻译： 描述了具有用于减少抖动的综合眼图打开功能的收发器模块。 收发器模块可以包括集成在单个电路中的发射器眼睛开启器和接收器眼睛开启器。 收发器模块还可以包括串行控制和各种其它集成组件。 可以集成在收发器模块上的其他功能包括环回模式，旁路功能，误码率测试和掉电模式。

    Transceiver module and integrated circuit with dual eye openers
    6.
    发明授权
    Transceiver module and integrated circuit with dual eye openers 有权
    收发模块和集成电路与双眼开启

    公开(公告)号：US07486894B2

    公开(公告)日：2009-02-03

    申请号：US10420027

    申请日：2003-04-17

    申请人： Lewis B. Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    发明人： Lewis B. Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    IPC分类号： H04B10/00

    CPC分类号： H04B10/40 ,  H04L7/033 ,  H04L25/242

    摘要： A transceiver module having integrated eye diagram opening functionality for reducing jitter is described. The transceiver module may include a transmitter eye opener and a receiver eye opener integrated in a single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modes, bypass features, bit error rate testing, and power down modes.

    摘要翻译： 描述了具有用于减少抖动的综合眼图打开功能的收发器模块。 收发器模块可以包括集成在单个电路中的发射器眼睛开启器和接收器眼睛开启器。 收发器模块还可以包括串行控制和各种其它集成组件。 可以集成在收发器模块上的其他功能包括环回模式，旁路功能，误码率测试和掉电模式。

    Integrated circuit with dual eye openers
    9.
    发明授权
    Integrated circuit with dual eye openers 有权
    带双眼开启器的集成电路

    公开(公告)号：US07099382B2

    公开(公告)日：2006-08-29

    申请号：US10629725

    申请日：2003-07-28

    申请人： Lewis B. Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    发明人： Lewis B. Aronson ,  Rudy Hofmeister ,  Christopher Madden ,  Mark Farley ,  Dan Case ,  Tom Lenosky

    IPC分类号： H04B1/38

    CPC分类号： H04B10/40 ,  H04L7/033 ,  H04L25/242

    摘要： A transceiver module having integrated eye diagram opening functionality for reducing jitter is described. The transceiver module may include a transmitter eye opener and a receiver eye opener integrated in a single circuit. The transceiver module may also include serial control and various other integrated components. Other functionalities that may be integrated on the transceiver module include loopback modes, bypass features, bit error rate testing, and power down modes.

    摘要翻译： 描述了具有用于减少抖动的综合眼图打开功能的收发器模块。 收发器模块可以包括集成在单个电路中的发射器眼睛开启器和接收器眼睛开启器。 收发器模块还可以包括串行控制和各种其它集成组件。 可以集成在收发器模块上的其他功能包括环回模式，旁路功能，误码率测试和掉电模式。

    Method and apparatus for estimating random jitter (RJ) and deterministic jitter (DJ) from bit error rate (BER)
    10.
    发明申请
    Method and apparatus for estimating random jitter (RJ) and deterministic jitter (DJ) from bit error rate (BER) 有权
    用于从误码率（BER）估计随机抖动（RJ）和确定性抖动（DJ）的方法和装置

    公开(公告)号：US20060059392A1

    公开(公告)日：2006-03-16

    申请号：US10939028

    申请日：2004-09-10

    申请人： Jade Kizer ,  Christopher Madden

    发明人： Jade Kizer ,  Christopher Madden

    IPC分类号： G06F11/00

    CPC分类号： G06F11/004 ,  G01R31/31709 ,  G01R31/3171 ,  G11C29/022

    摘要： An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled. In an embodiment of the present invention, the first and second counters are logarithmic counters that include overflow protection. The counter values are output to a processing device to perform the BER calculation in an embodiment of the present invention. A plurality of BER values is then obtained for corresponding offsets. A subset of the plurality of BER values corresponding to the plurality of offsets is selected. An inverse of the standard normal cumulative distribution (NormSlnv) function for respective BER values is calculated. Two linear fits on the transformed BER values and offsets are performed to obtain the x-intercepts that correspond to a DJ component and the slopes corresponding to a RJ component. The DJ and RJ components are used with the Fibre Channel jitter model equation to predict BER as a function of transition density and offset value.

    摘要翻译： 一种装置和方法提供了对诸如处理器和存储器装置的IC之间的接口的BER的预测，而不使用特殊的测试设备。 已知的数据模式或PRBS被发送到接收机，接收机将接收到的数据值与期望的数据值进行比较，以确定在本发明的实施例中是否发生了位错误。 数据眼的中心和数据眼的边缘被采样（过采样），以便确定在本发明的替代实施例中是否发生位错误。 第一计数器用于对采样的总位数进行计数，第二计数器用于对所采样总位数中发生的错误数进行计数。 在本发明的实施例中，第一和第二计数器是包括溢出保护的对数计数器。 在本发明的实施例中，计数器值被输出到处理装置以执行BER计算。 然后对于相应的偏移获得多个BER值。 选择与多个偏移对应的多个BER值的子集。 计算相应BER值的标准正态累积分布（NormSlnv）函数的倒数。 执行对经变换的BER值和偏移的两个线性拟合以获得对应于DJ分量的x截距和对应于RJ分量的斜率。 DJ和RJ组件与光纤通道抖动模型方程一起用于预测BER作为转换密度和偏移值的函数。