公开(公告)号：US20120047414A1

公开(公告)日：2012-02-23

申请号：US12892199

申请日：2010-09-28

申请人： SHUENN-GI LEE ,  CHUNG HSUAN WANG ,  WERN-HO SHEEN

发明人： SHUENN-GI LEE ,  CHUNG HSUAN WANG ,  WERN-HO SHEEN

IPC分类号： H03M13/05 ,  G06F11/08

CPC分类号： H03M13/2739 ,  H03M13/2764 ,  H03M13/2775

摘要： An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function Π(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0≦i≦k−1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where Π(i) is also a ith interleaving address generated by the apparatus.

摘要翻译： 二次置换多项式（QPP）交织器的地址生成装置接收多个可配置参数，并使用多个QPP单元根据QPP函数＆Pgr计算并输出多个交织地址;（i）=（f1i + f2i2）mod k ，其中f1和f2是QPP系数，k是输入序列的信息块长度，0＆nlE; i＆nlE; k-1，mod是模运算。 多个QPP单元中的每一个是并行计算单元，并且并行地输出相应的交织器地址组，其中＆amp;（i）也是由该设备生成的第i个交织地址。

公开(公告)号：US08060796B2

公开(公告)日：2011-11-15

申请号：US11864992

申请日：2007-09-29

申请人： Chung-Hsuan Wang ,  Shuenn-Gi Lee

发明人： Chung-Hsuan Wang ,  Shuenn-Gi Lee

IPC分类号： G06F11/00

CPC分类号： H04L1/007 ,  H03M13/1102 ,  H03M13/2957 ,  H03M13/356 ,  H03M13/6368 ,  H03M13/6375 ,  H04L1/0069

摘要： A multiplexing method for data switching is disclosed. In the method, a continuous data is received, and the continuous data includes a plurality of super frames, and each super frame includes a plurality of frames. These super frames are divided into a set of even super frames and a set of odd super frames. The frames included in the set of odd super frames are sorted by corresponding required bit error rate of each frame decreasingly or increasingly. The frames included in the set of even super frames are sorted by the required bit error rate of each frame increasingly or decreasingly. An encoder is used to encode these sorted super frames.

摘要翻译： 公开了一种用于数据切换的复用方法。 在该方法中，接收连续数据，连续数据包括多个超帧，每个超帧包括多个帧。 这些超帧被分成一组偶数超帧和一组奇数超帧。 包含在奇数超帧组中的帧按照每个帧的相应所需的误码率逐渐或逐渐地排序。 包含在一组偶数超帧中的帧按照每个帧的所需比特错误率逐渐或逐渐地排序。 编码器用于对这些排序的超帧进行编码。

公开(公告)号：US08332701B2

公开(公告)日：2012-12-11

申请号：US12647394

申请日：2009-12-25

申请人： Shuenn-Gi Lee ,  Chung-Hsuan Wang ,  Wern-Ho Sheen

发明人： Shuenn-Gi Lee ,  Chung-Hsuan Wang ,  Wern-Ho Sheen

IPC分类号： G06F11/00

CPC分类号： H03M13/2771 ,  H03M13/2739 ,  H03M13/2764 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/6525 ,  H03M13/6561

摘要： An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function Π(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein Π(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0≦i≦k−1.

摘要翻译： 提供了一种用于二次置换多项式（QPP）交织器的地址生成装置。 它包括一个基本递归单元，和由递归单位表示的L个递归单元，直到第L个递归单元。 该设备根据QPP功能＆Pgr输入多个可配置参数;（i）=（f1i + f2i2）mod k，经由基本递归单元串行生成多个交织器地址，并通过以下方式生成L组对应的交织器地址 第一个到第L个递归单元，其中＆Pgr;（i）是由装置生成的第i个交织器地址，f1和f2是QPP系数，k是输入序列的信息块长度，0＆nlE; i＆nlE; k -1。

公开(公告)号：US20110066914A1

公开(公告)日：2011-03-17

申请号：US12647394

申请日：2009-12-25

申请人： Shuenn-Gi Lee ,  Chung-Hsuan Wang ,  Wern-Ho Sheen

发明人： Shuenn-Gi Lee ,  Chung-Hsuan Wang ,  Wern-Ho Sheen

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/2771 ,  H03M13/2739 ,  H03M13/2764 ,  H03M13/2957 ,  H03M13/3972 ,  H03M13/6525 ,  H03M13/6561

摘要： An address generation apparatus for a quadratic permutation polynomial (QPP) interleaver is provided. It comprises a basic recursive unit, and L recursive units represented by first recursive unit up to Lth recursive units. The apparatus inputs a plurality of configurable parameters according to a QPP function Π(i)=(f1i+f2i2) mod k, generates a plurality of interleaver addresses in serial via the basic recursive unit, and generates L groups of corresponding interleaver addresses via the first up to the Lth recursive units, wherein Π(i) is the i-th interleaver address generated by the apparatus, f1 and f2 are QPP coefficients, and k is information block length of an input sequence, 0≦i≦k−1.

摘要翻译： 提供了一种用于二次置换多项式（QPP）交织器的地址生成装置。 它包括一个基本递归单元，和由递归单位表示的L个递归单元，直到第L个递归单元。 该设备根据QPP功能＆Pgr输入多个可配置参数;（i）=（f1i + f2i2）mod k，经由基本递归单元串行生成多个交织器地址，并通过以下方式生成L组对应的交织器地址 第一个到第L个递归单元，其中＆Pgr;（i）是由装置生成的第i个交织器地址，f1和f2是QPP系数，k是输入序列的信息块长度，0＆nlE; i＆nlE; k -1。

公开(公告)号：US08468410B2

公开(公告)日：2013-06-18

申请号：US12892199

申请日：2010-09-28

申请人： Shuenn-Gi Lee ,  Chung Hsuan Wang ,  Wern-Ho Sheen

发明人： Shuenn-Gi Lee ,  Chung Hsuan Wang ,  Wern-Ho Sheen

IPC分类号： G06F11/00

CPC分类号： H03M13/2739 ,  H03M13/2764 ,  H03M13/2775

摘要： An address generation apparatus for quadratic permutation polynomial (QPP) interleaver receives several configurable parameters and uses a plurality of QPP units to compute and outputs a plurality of interleaving addresses according to a QPP function Π(i)=(f1i+f2i2) mod k, where f1 and f2 are QPP coefficients, k is information block length of an input sequence, 0≦i≦k−1, and mod is a modulus operation. Each of the plurality of QPP units is a parallel computation unit, and outputs in parallel a corresponding group of interleaver addresses, where Π(i) is also a ith interleaving address generated by the apparatus.

摘要翻译： 二次置换多项式（QPP）交织器的地址生成装置接收多个可配置参数，并使用多个QPP单元根据QPP函数Pi（i）=（f1i + f2i2）mod k来计算并输出多个交织地址， 其中f1和f2是QPP系数，k是输入序列的信息块长度，0 @ i k-1，mod是模运算。 多个QPP单元中的每一个是并行计算单元，并且并行地输出对应的交织器组地址，其中Pi（i）也是由该装置生成的第i个交织地址。

公开(公告)号：US20090016352A1

公开(公告)日：2009-01-15

申请号：US11864992

申请日：2007-09-29

申请人： Chung-Hsuan Wang ,  Shuenn-Gi Lee

发明人： Chung-Hsuan Wang ,  Shuenn-Gi Lee

IPC分类号： H04L12/56

CPC分类号： H04L1/007 ,  H03M13/1102 ,  H03M13/2957 ,  H03M13/356 ,  H03M13/6368 ,  H03M13/6375 ,  H04L1/0069

摘要： A multiplexing method for data switching is disclosed. In the method, a continuous data is received, and the continuous data includes a plurality of super frames, and each super frame includes a plurality of frames. These super frames are divided into a set of even super frames and a set of odd super frames. The frames included in the set of odd super frames are sorted by corresponding required bit error rate of each frame decreasingly or increasingly. The frames included in the set of even super frames are sorted by the required bit error rate of each frame increasingly or decreasingly. An encoder is used to encode these sorted super frames.

摘要翻译： 公开了一种用于数据切换的复用方法。 在该方法中，接收连续数据，连续数据包括多个超帧，每个超帧包括多个帧。 这些超帧被分成一组偶数超帧和一组奇数超帧。 包含在奇数超帧组中的帧按照每个帧的相应所需的误码率逐渐或逐渐地排序。 包含在一组偶数超帧中的帧按照每个帧的所需比特错误率逐渐或逐渐地排序。 编码器用于对这些排序的超帧进行编码。