公开(公告)号：US06888743B2

公开(公告)日：2005-05-03

申请号：US10331058

申请日：2002-12-27

Applicant: Mark A. Durlam ,  Thomas W. Andre ,  Brian R. Butcher ,  Mark F. Deherrera ,  Bradley N. Engel ,  Bradley J. Garni ,  Gregory W. Grynkewich ,  Joseph J. Nahas ,  Nicholas D. Rizzo ,  Saied Tehrani ,  Clarance J. Tracy

Inventor： Mark A. Durlam ,  Thomas W. Andre ,  Brian R. Butcher ,  Mark F. Deherrera ,  Bradley N. Engel ,  Bradley J. Garni ,  Gregory W. Grynkewich ,  Joseph J. Nahas ,  Nicholas D. Rizzo ,  Saied Tehrani ,  Clarance J. Tracy

IPC: G11C11/15 ,  G11C11/02

CPC classification number: G11C11/16

Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

Abstract translation: 提供了一种减少隔离晶体管数量的MRAM架构。 MRAM架构包括电耦合以形成有组合的存储单元的磁阻存储单元。 组合存储单元的磁阻存储单元由磁隧道结（MTJ）形成，并且形成为没有隔离器件，例如隔离晶体管，并且编程线和位线与每个磁阻存储器单元相邻。 优选地，联动存储单元的磁阻存储单元仅包括MTJ，并且编程线和位线与每个磁阻存储单元相邻。