公开(公告)号：US20090085058A1

公开(公告)日：2009-04-02

申请号：US11864409

申请日：2007-09-28

Applicant: Phillip G. Mather ,  Sanjeev Aggarwal ,  Brian R. Butcher ,  Renu W. Dave ,  Frederick B. Mancoff ,  Nicholas D. Rizzo

Inventor： Phillip G. Mather ,  Sanjeev Aggarwal ,  Brian R. Butcher ,  Renu W. Dave ,  Frederick B. Mancoff ,  Nicholas D. Rizzo

IPC: H01L29/82 ,  H01L21/46

CPC classification number: H01L43/08 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/161 ,  H01L43/12

Abstract: A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.

Abstract translation: 形成电子器件的工艺可以包括形成包括隧道势垒层的堆叠。 隧道阻挡层可以具有大于化学计量比的金属原子与氧原子的比例，其中该比率具有特定值。 该方法还可以包括形成具有能够吸收氧的组成的吸气层，以及在吸气层上沉积绝缘层。 该方法还可以包括将绝缘层暴露于至少约60℃的温度。在一个实施方案中，在这种曝光之后，将一部分吸气层转化为绝缘材料。 在另一个实施例中，电子设备可以包括磁性隧道结和位于另一绝缘层的开口内的相邻绝缘层。

公开(公告)号：US07445943B2

公开(公告)日：2008-11-04

申请号：US11584411

申请日：2006-10-19

Applicant: Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

Inventor： Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

IPC: H01L21/00

CPC classification number: H01L43/12

Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.

Abstract translation: 提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。 该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层 ，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及 位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。 在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。 获得了提高的产量和性能。

公开(公告)号：US07169622B2

公开(公告)日：2007-01-30

申请号：US10912979

申请日：2004-08-05

Applicant: Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Clarence J. Tracy

Inventor： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Clarence J. Tracy

IPC: H01L21/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  H01L27/228

Abstract: Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.

Abstract translation: 制造磁阻随机存取存储器单元和用于磁阻随机存取存储单元的结构开始于提供其中形成有晶体管的衬底。 形成电耦合到晶体管的接触元件，并且电介质材料沉积在由接触元件部分界定的区域内。 在电介质材料内形成数字线，数字线覆盖接触元件的一部分。 导电层形成在数字线上方并与接触元件电连通。

公开(公告)号：US06518071B1

公开(公告)日：2003-02-11

申请号：US10109429

申请日：2002-03-28

Applicant: Mark A. Durlam ,  Mark F. Deherrera ,  Kelly W. Kyler ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Steven M. Smith ,  Charles Snyder ,  Jon M. Slaughter

Inventor： Mark A. Durlam ,  Mark F. Deherrera ,  Kelly W. Kyler ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Steven M. Smith ,  Charles Snyder ,  Jon M. Slaughter

IPC: H01L2100

CPC classification number: H01L43/12

Abstract: A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.

Abstract translation: 一种制造具有锥形的MRAM器件的方法，包括以下步骤：提供衬底，形成位于衬底上的电介质区域，对介质区域进行图案化和各向同性地蚀刻到衬底以形成沟槽，将MRAM器件沉积在 沟槽，其中MRAM器件包括位于衬底上的宽度的第一铁磁区域，具有位于第一铁磁区域上的宽度的非铁磁间隔层，以及位于非铁磁间隔层上的宽度的第二铁磁区域 其中所述锥形通过使所述第一铁磁性区域的宽度大于所述非铁磁间隔层的宽度而形成，并且所述非铁磁隔离层的宽度大于所述第二铁磁区域的宽度，使得所述第一铁磁性区域 区域与第二铁磁区域分离。

公开(公告)号：US20100197043A1

公开(公告)日：2010-08-05

申请号：US12363404

申请日：2009-01-30

Applicant: Nicholas D. RIZZO ,  Kenneth H. SMITH ,  Sanjeev AGGARWAL ,  Anthony CIANCIO ,  Brian R. BUTCHER ,  Kelly Wayne KYLER

Inventor： Nicholas D. RIZZO ,  Kenneth H. SMITH ,  Sanjeev AGGARWAL ,  Anthony CIANCIO ,  Brian R. BUTCHER ,  Kelly Wayne KYLER

IPC: H01L21/00

CPC classification number: H01L27/222 ,  G11C11/161 ,  G11C11/1659 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/978 ,  H01L2924/00

Abstract: A method of forming a magnetoelectronic device includes forming a dielectric material (114) surrounding a magnetic bit (112), etching the dielectric material (114) to define an opening (122) over the magnetic bit (112) without exposing the magnetic bit (112), the opening (122) having a sidewall, depositing a blanket layer (132) of cladding material over the dielectric material (118), including over the sidewall, removing by a sputtering process the blanket layer (132) in the bottom of the opening (122) and the dielectric material (124) over the magnetic bit (112), and forming a conductive material (146) within the opening (122) to form a bit line (154). This process reduces errors caused by process irregularities such as edges of the bits (112) protruding and thereby causing defects in the cladding layer (132) formed thereover. A bit line or digit line so formed may optionally be tapered at the ends (182, 184) to prevent magnetic reversal of the bit line magnetic moment that otherwise may occur due to external magnetic fields.

Abstract translation: 一种形成磁电子器件的方法包括形成围绕磁头（112）的电介质材料（114），蚀刻电介质材料（114）以在磁头（112）上方限定开口（122），而不暴露磁头 112），所述开口（122）具有侧壁，在所述电介质材料（118）上沉积包覆材料的覆盖层（132），包括在所述侧壁上方，通过溅射工艺去除所述绝缘层 所述开口（122）和所述电介质材料（124）在所述磁头（112）上方，并且在所述开口（122）内形成导电材料（146）以形成位线（154）。 该过程减少了诸如位（112）的边缘突出的过程不规则性引起的错误，从而在其上形成的包层（132）中产生缺陷。 如此形成的位线或数字线可以可选地在端部（182,184）处是锥形的，以防止由于外部磁场而可能发生的位线磁矩的磁性反转。

公开(公告)号：US07602177B2

公开(公告)日：2009-10-13

申请号：US11584473

申请日：2006-10-19

Applicant: Brian R. Butcher ,  Kenneth H. Smith ,  Bradley N. Engel

Inventor： Brian R. Butcher ,  Kenneth H. Smith ,  Bradley N. Engel

IPC: G01R33/02

CPC classification number: G01R33/06

Abstract: An apparatus (46, 416, 470) is provided for sensing physical parameters. The apparatus (46, 416, 470) comprises a magnetic tunnel junction (MTJ) (32, 432), first and second electrodes (36, 38, 426, 434), a magnetic field source (MFS) (34, 445, 476) whose magnetic field (35) overlaps the MTJ (32, 432) and a moveable magnetic cladding element (33, 448, 478) whose proximity (43, 462, 479, 479′) to the MFS (34, 445, 476) varies in response to an input to the sensor. The MFS (34, 445, 476) is located between the cladding element (33, 448, 478) and the MTJ (32, 432). Motion (41, 41′, 41-1, 464, 477) of the cladding element (33, 448, 478) relative to the MFS (34, 445, 476) in response to sensor input causes the magnetic field (35) at the MTJ (32, 432) to change, thereby changing the electrical properties of the MTJ (32, 432). A one-to-one correspondence (54) between the sensor input and the electrical properties of the MTJ (32, 432) is obtained.

Abstract translation: 提供了一种用于感测物理参数的装置（46,416,470）。 装置（46,416,470）包括磁性隧道结（MTJ）（32,432），第一和第二电极（36,38,426,434），磁场源（MFS）（34,445,476） ），其磁场（35）与MTJ（32,432）重叠，以及可移动的磁性包覆元件（33,448,478），其与MFS（34,445,476）接近的距离（43,446,479,479） 响应于传感器的输入而变化。 MFS（34,445,476）位于包层元件（33,448,478）和MTJ（32,432）之间。 响应于传感器输入，相对于MFS（34,445,476），包层元件（33,448,478）的运动（41,41'，41-1,446,477）使磁场（35）在 MTJ（32,432）改变，从而改变MTJ（32,432）的电性能。 获得传感器输入和MTJ（32,432）的电气特性之间的一一对应（54）。

公开(公告)号：US07476329B2

公开(公告)日：2009-01-13

申请号：US11050191

申请日：2005-02-02

Applicant: Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Kelly Kyler ,  Charles A. Synder ,  Kenneth H. Smith ,  Clarence J. Tracy ,  Richard Williams

Inventor： Gregory W. Grynkewich ,  Brian R. Butcher ,  Mark A. Durlam ,  Kelly Kyler ,  Charles A. Synder ,  Kenneth H. Smith ,  Clarence J. Tracy ,  Richard Williams

IPC: H01L21/00

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/15 ,  H01L43/12

Abstract: A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Abstract translation: 用于使覆盖磁电元件的导电层接触的方法包括形成覆盖电介质区域的存储元件层。 沉积在存储元件层上的第一导电层。 第一电介质层沉积在第一导电层上，并被图案化和蚀刻以形成第一掩模层。 使用第一掩模层，蚀刻第一导电层。 沉积第二介电层，覆盖第一掩模层和电介质区域。 去除第二介电层的一部分以露出第一掩模层。 对第二介电层和第一掩模层进行蚀刻化学处理，使得以比第二介电层更快的速率蚀刻第一掩模层。 蚀刻暴露第一导电层。

公开(公告)号：US20080160640A1

公开(公告)日：2008-07-03

申请号：US11649094

申请日：2007-01-03

Applicant: Brian R. Butcher ,  Kerry J. Nagel ,  Kenneth H. Smith

Inventor： Brian R. Butcher ,  Kerry J. Nagel ,  Kenneth H. Smith

IPC: H01L21/00

CPC classification number: H01L43/12 ,  Y10S438/975

Abstract: According to an example embodiment, a semiconductor device includes a lower electrode (316) disposed on an oxide layer (302), an upper electrode (320) disposed on the lower electrode, a dielectric pattern (322) disposed on the oxide layer and surrounding the upper electrode, the upper electrode protruding above an upper surface of the dielectric pattern, and a contact pattern (328) that is contiguous with the upper electrode and the dielectric pattern.

Abstract translation: 根据示例性实施例，半导体器件包括设置在氧化物层（302）上的下电极（316），设置在下电极上的上电极（320），设置在氧化物层上的电介质图案（322） 上电极，突出在电介质图案的上表面上方的上电极以及与上电极和电介质图案相邻的接触图案（328）。

公开(公告)号：US20080096290A1

公开(公告)日：2008-04-24

申请号：US11584411

申请日：2006-10-19

Applicant: Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

Inventor： Kenneth H. Smith ,  Brian R. Butcher ,  Gregory W. Grynkewich ,  Srinivas V. Pietambaram ,  Nicholas D. Rizzo

IPC: H01L21/00

CPC classification number: H01L43/12

Abstract: Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.

Abstract translation: 提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。 该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层 ，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及 位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。 在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。 获得了提高的产量和性能。

公开(公告)号：US06888743B2

公开(公告)日：2005-05-03

申请号：US10331058

申请日：2002-12-27

Applicant: Mark A. Durlam ,  Thomas W. Andre ,  Brian R. Butcher ,  Mark F. Deherrera ,  Bradley N. Engel ,  Bradley J. Garni ,  Gregory W. Grynkewich ,  Joseph J. Nahas ,  Nicholas D. Rizzo ,  Saied Tehrani ,  Clarance J. Tracy

Inventor： Mark A. Durlam ,  Thomas W. Andre ,  Brian R. Butcher ,  Mark F. Deherrera ,  Bradley N. Engel ,  Bradley J. Garni ,  Gregory W. Grynkewich ,  Joseph J. Nahas ,  Nicholas D. Rizzo ,  Saied Tehrani ,  Clarance J. Tracy

IPC: G11C11/15 ,  G11C11/02

CPC classification number: G11C11/16

Abstract: An MRAM architecture is provided that reduces the number of isolation transistors. The MRAM architecture includes magnetoresistive memory cells that are electrically coupled to form a ganged memory cell. The magnetoresistive memory cells of the ganged memory cell are formed with Magnetic Tunnel Junctions (MTJs) and formed without isolation devices, such as isolation transistors, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells. Preferably, the magnetoresistive memory cells of the ganged memory cell only include MTJs, and a programming line and a bit line are adjacent to each of the magnetoresistive memory cells.

Abstract translation: 提供了一种减少隔离晶体管数量的MRAM架构。 MRAM架构包括电耦合以形成有组合的存储单元的磁阻存储单元。 组合存储单元的磁阻存储单元由磁隧道结（MTJ）形成，并且形成为没有隔离器件，例如隔离晶体管，并且编程线和位线与每个磁阻存储器单元相邻。 优选地，联动存储单元的磁阻存储单元仅包括MTJ，并且编程线和位线与每个磁阻存储单元相邻。