公开(公告)号：US06249520B1

公开(公告)日：2001-06-19

申请号：US08957664

申请日：1997-10-24

申请人： Simon C. Steely, Jr. ,  Stephen R. VanDoren ,  Madhumitra Sharma ,  Craig D. Keefer ,  David W. Davis

发明人： Simon C. Steely, Jr. ,  Stephen R. VanDoren ,  Madhumitra Sharma ,  Craig D. Keefer ,  David W. Davis

IPC分类号： H04L1250

CPC分类号： G06F13/4022 ,  G06F12/0826 ,  G06F15/17393

摘要： An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory. Memory performance is additionally improved by including, at each memory, a delayed write buffer which is used in conjunction with the directory to identify victims that are to be written to memory. An arb bus coupled to the output of the directory of each node provides a central ordering point for all messages that are transferred through the SMP. The messages comprise a number of transactions, and each transaction is assigned to a number of different virtual channels, depending upon the processing stage of the message. The use of virtual channels thus helps to maintain data coherency by providing a straightforward method for maintaining system order. Using the virtual channels and the directory structure, cache coherency problems that would previously result in deadlock may be avoided.

摘要翻译： 用于大SMP计算机系统的架构和一致性协议包括分层交换结构，其允许多个多处理器节点耦合到交换机以以最佳性能进行操作。 在每个多处理器节点内，提供同时缓冲系统，其允许多处理器节点的所有处理器以最高性能运行。 存储器在节点之间共享，存储器的一部分驻留在每个多处理器节点处。 每个多处理器节点包括用于维持存储器一致性的多个元件，包括受害缓存，目录和事务跟踪表。 受害者缓存允许选择性地更新目的地存储在远程多处理节点处的存储器的受害者数据，从而提高存储器的整体性能。 通过在每个存储器处包括延迟的写入缓冲器来进一步改善存储器性能，该缓冲器与目录一起使用以识别要写入存储器的受害者。 耦合到每个节点的目录的输出的arb总线为通过SMP传输的所有消息提供了中心排序点。 消息包括多个事务，并且根据消息的处理阶段，将每个事务分配给多个不同的虚拟通道。 因此，通过提供用于维护系统顺序的简单方法，使用虚拟通道有助于维持数据一致性。 使用虚拟通道和目录结构，可以避免先前导致死锁的高速缓存一致性问题。