公开(公告)号：US20190220420A1

公开(公告)日：2019-07-18

申请号：US16328044

申请日：2016-09-30

申请人： INTEL CORPORATION

发明人： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Robert G. Blankenship ,  Raj K. Ramanujan

IPC分类号： G06F12/14 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/50 ,  G06F12/0808

CPC分类号： G06F12/1425 ,  G06F9/50 ,  G06F9/5016 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0826 ,  G06F12/0831 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/154

摘要： Examples may include techniques to enable cache coherency of objects in a distributed shared memory (DSM) system, even where multiple nodes in the system manage the objects. Node memory space includes a tracking address space (TAS) where lines in the TAS correspond to objects in the (DSM). Access to the objects and the TAS is managed by a host fabric interface (HFI) caching agent in HFI of a node.

公开(公告)号：US09601199B2

公开(公告)日：2017-03-21

申请号：US12842958

申请日：2010-07-23

申请人： David R. Cheriton ,  Amin Firoozshahian ,  Alexandre Y. Solomatnikov

发明人： David R. Cheriton ,  Amin Firoozshahian ,  Alexandre Y. Solomatnikov

IPC分类号： G11C15/00

CPC分类号： G06F12/0811 ,  G06F12/0826 ,  G06F12/0862 ,  G06F2212/283 ,  G06F2212/602 ,  G06F2212/622 ,  G11C15/00

摘要： Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain.Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element. A local state associated with a selected iterator register is generated by performing one or more register operations relating to the selected iterator register and involving pointers in the pointer fields of the selected iterator register. A pointer-linked data structure is updated in the memory system according to the local state.

公开(公告)号：US09274961B2

公开(公告)日：2016-03-01

申请号：US14534842

申请日：2014-11-06

申请人： INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD

发明人： Endong Wang ,  Leijun Hu ,  Jicheng Chen ,  Dong Zhang ,  Weifeng Gong ,  Feng Zhang

IPC分类号： G06F12/08 ,  G06F15/173

CPC分类号： G06F12/0822 ,  G06F12/082 ,  G06F12/0826 ,  G06F15/17368 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/2542 ,  G06F2212/622

摘要： A method for building a multi-processor system with nodes having multiple cache coherency domains. In this system, a directory built in a node controller needs to include processor domain attribute information, and the information can be acquired by configuring cache coherency domain attributes of ports of the node controller connected to processors. In the disclosure herein, the node controller can support the multiple physical cache coherency domains in a node.

摘要翻译： 一种用于构建具有多个高速缓存一致性域的节点的多处理器系统的方法。 在该系统中，构建在节点控制器中的目录需要包括处理器域属性信息，并且可以通过配置连接到处理器的节点控制器的端口的高速缓存一致性域属性来获取信息。 在本文的公开内容中，节点控制器可以支持节点中的多个物理高速缓存一致性域。

公开(公告)号：US20150143050A1

公开(公告)日：2015-05-21

申请号：US14085106

申请日：2013-11-20

申请人： Netspeed Systems

发明人： Joe ROWLANDS ,  Sailesh KUMAR

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F9/50 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/082 ,  G06F12/0826 ,  G06F12/0828

摘要： The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory.

摘要翻译： 本申请涉及提供配置为维护多个条目的目录的控制电路，其中每个条目可以指示由多个代理/主机共享诸如高速缓存行的资源。 当与代理商共享与一个或多个条目相对应的资源时，本发明的控制电路还可以提供具有第一格式的一个或多个条目与具有第二格式的单个条目的合并。 第一格式可以包括表示代理之一的地址和指针，并且第二格式可以包括指示多于一个代理的共享向量。 在另一方面，第二格式可以利用，并入和/或表示可以基于目录中的位置指示一个或多个资源的多个条目。

公开(公告)号：US20150121009A1

公开(公告)日：2015-04-30

申请号：US14516192

申请日：2014-10-16

申请人： Advanced Micro Devices, Inc.

发明人： Wade K. Smith

IPC分类号： G06F12/10 ,  G06F12/08

CPC分类号： G06F12/1009 ,  G06F12/0811 ,  G06F12/0826 ,  G06F2212/622 ,  G06F2212/652

摘要： A device for and method of storing page table entries in a first cache. A first page table entry is received having a fragment field that contains address information for a requested first page and at least a second page logically adjacent to the first page. A second page table entry is generated from the first page table entry to be stored with the first page table entry. The second page table entry provides address information for the second page. The second page table entry has a configuration that is compatible with the first cache.

摘要翻译： 用于将页表条目存储在第一高速缓存中的装置和方法。 接收到具有片段字段的第一页表条目，该片段字段包含所请求的第一页的地址信息和与第一页逻辑上相邻的至少第二页。 从第一页表条目生成第二页表条目以与第一页表条目一起存储。 第二页表项提供第二页的地址信息。 第二页表条目具有与第一高速缓存兼容的配置。

公开(公告)号：US08930640B2

公开(公告)日：2015-01-06

申请号：US12322807

申请日：2009-02-06

申请人： Jordan Chicheportiche ,  Said Derradji

发明人： Jordan Chicheportiche ,  Said Derradji

IPC分类号： G06F13/00 ,  G06F12/08

CPC分类号： G06F12/0826 ,  G06F12/0817

摘要： The invention has application in implementation of large Symmetric Multiprocessor Systems with a large number of nodes which include processing elements and associated cache memories. The illustrated embodiment of the invention provides for interconnection of a large number of multiprocessor nodes while reducing over the prior art the size of directories for tracking of memory coherency throughout the system. The embodiment incorporates within the memory controller of each node, directory information relating to the current locations of memory blocks which allows for elimination at a higher level in the node controllers of a larger volume of directory information relating to the location of memory blocks. This arrangement thus allows for more efficient implementation of very large multiprocessor computer systems.

公开(公告)号：US08812765B2

公开(公告)日：2014-08-19

申请号：US13848546

申请日：2013-03-21

申请人： Silicon Graphics International Corp.

发明人： Donglai Dai ,  Randal Passint

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F3/06

CPC分类号： G06F3/0644 ,  G06F12/0817 ,  G06F12/0826

摘要： A method for maintaining data coherency in a shared-memory computer system having a plurality of nodes divides the local memory of a given node into one or more blocks and stores a data record for each block indicating a plurality of node groups and a selection of the node groups. Each selected node group represents a number of nodes, and selected node groups represent at least one node that has requested access to the block. In response to receiving an access request from a requesting node that may or may not be in a selected node group, the method and system update the data record to indicate the correct selection. If the requesting node is not in any node group, the data record is adjusted to have new node groups, one of which represents the requesting node.

摘要翻译： 一种用于在具有多个节点的共享存储器计算机系统中维持数据一致性的方法将给定节点的本地存储器划分为一个或多个块，并且存储指示多个节点组的每个块的数据记录，并且选择 节点组。 每个选定的节点组表示多个节点，并且所选择的节点组表示至少一个请求访问该块的节点。 响应于从请求节点接收到可能选择的节点组或可能不在所选节点组中的访问请求，该方法和系统更新数据记录以指示正确的选择。 如果请求节点不在任何节点组中，则将数据记录调整为具有新的节点组，其中一个表示请求节点。

公开(公告)号：US20140032848A1

公开(公告)日：2014-01-30

申请号：US13607290

申请日：2012-09-07

申请人： Hongzhou ZHAO ,  Arrvindh SHRIRAMAN ,  Sandhya DWARKADAS

发明人： Hongzhou ZHAO ,  Arrvindh SHRIRAMAN ,  Sandhya DWARKADAS

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/082 ,  G06F12/0826 ,  G06F2212/1044

摘要： A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry.

摘要翻译： 提供了识别和表示应用中存在的共享模式的子集的方法和目录系统。 如本文所使用的，术语共享模式是指访问应用中的单个存储器位置的一组处理器。 共享模式与每个高速缓存行分离并保存在单独的目录表中。 缓存块的共享模式是表示共享块的处理器的位向量。 具有相同共享模式的多个高速缓存行指向目录表中的公用条目。 此外，当超过表容量时，彼此相似的模式被动态整理为单个条目。

公开(公告)号：US08230178B2

公开(公告)日：2012-07-24

申请号：US11055483

申请日：2005-02-10

申请人： James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Jeffrey Adam Stuecheli

发明人： James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke ,  Jeffrey Adam Stuecheli

IPC分类号： G06F12/00

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F12/0826

摘要： In a cache coherent data processing system including at least first and second coherency domains, a memory block is stored in a system memory in association with a domain indicator indicating whether or not the memory block is cached, if at all, only within the first coherency domain. A master in the first coherency domain determines whether or not a scope of broadcast transmission of an operation should extend beyond the first coherency domain by reference to the domain indicator stored in the cache and then performs a broadcast of the operation within the cache coherent data processing system in accordance with the determination.

摘要翻译： 在包括至少第一和第二相干域的缓存相干数据处理系统中，存储器块与指示是否缓存存储器块的域指示符相关联地存储在系统存储器中，如果有的话，只有在第一一致性内 域。 第一相干域中的主设备通过参考存储在高速缓存中的域指示符来确定操作的广播传输的范围是否应超出第一相关域，然后在高速缓存相干数据处理中执行操作的广播 系统按照确定。

公开(公告)号：US07640401B2

公开(公告)日：2009-12-29

申请号：US11691007

申请日：2007-03-26

申请人： Benjamin Tsien

发明人： Benjamin Tsien

IPC分类号： G06F12/00

CPC分类号： G06F12/0826

摘要： In one embodiment, a first node comprises at least one memory request source and a node controller coupled to the memory request source. The node controller comprises a remote hit predictor configured to predict a second node to have a coherent copy of a block addressed by a memory request generated by the memory request source, and the node controller is configured to issued a speculative probe to the second node responsive to the prediction and to the memory request.

摘要翻译： 在一个实施例中，第一节点包括耦合到存储器请求源的至少一个存储器请求源和节点控制器。 节点控制器包括远程命中预测器，其被配置为预测第二节点具有由存储器请求源生成的存储器请求寻址的块的相干副本，并且节点控制器被配置为向第二节点发出推测性探测器 到预测和存储器请求。