公开(公告)号：US20210165675A1

公开(公告)日：2021-06-03

申请号：US16717889

申请日：2019-12-17

Applicant: Xiao Wang ,  Cunming Liang ,  Tiwei Bie ,  Zhihong Wang

Inventor： Xiao Wang ,  Cunming Liang ,  Tiwei Bie ,  Zhihong Wang

IPC: G06F9/455 ,  G06F11/34

Abstract: Methods and apparatus for live migration for hardware accelerated para-virtualized IO devices. In one aspect, a method is implemented on a host platform including a VMM or hypervisor hosting a VM with a guest OS and a hardware (HW) input/output (TO) device implemented as a para-virtualized IO device with hardware acceleration that is enabled to directly write data into guest memory using a direct memory access (DMA) data path via a HW accelerator. A relayed data path including a software (SW) relay is setup between the HW IO device and a guest IO device driver. During a live migration of the VM, the SW relay tracks memory pages in guest memory being written to by the HW IO device via the DMA data path and logs the memory pages being written to as dirty memory pages. Embodiments may employ Vhost Data Path Acceleration (VDPA) for virtio, as well as other para-virtualization components.

公开(公告)号：US20200183729A1

公开(公告)日：2020-06-11

申请号：US16738034

申请日：2020-01-09

Applicant: Xiuchun Lu ,  Cunming Liang ,  Shaopeng He ,  Nrupal Jani ,  Anjali Jain ,  Edwin Verplanke ,  Parthasarathy Sarangam ,  Zhirun Yan

Inventor： Xiuchun Lu ,  Cunming Liang ,  Shaopeng He ,  Nrupal Jani ,  Anjali Jain ,  Edwin Verplanke ,  Parthasarathy Sarangam ,  Zhirun Yan

IPC: G06F9/455 ,  G06F9/445

Abstract: Methods and apparatus for evolving hypervisor pass-through devices supporting platform independence through a core solution called MUSE (Mdev in User SpacE) that allows mediated pass-through device being served by software running in user space. The MUSE architecture supports platform hardware independence while providing pass-through performance similar to hardware-specific solutions and providing enhanced performance in virtualized environments using existing software components, including various operating systems and associated libraries for implementing SDN (Software Defined Networking) and VNF (Virtualized Network Function).

公开(公告)号：US20230236909A1

公开(公告)日：2023-07-27

申请号：US18127960

申请日：2023-03-29

Applicant: Kefei Zhang ,  Cunming Liang ,  Ping Yu ,  Qiming Liu ,  Xingping Ruan ,  Haiyue Wang ,  Xiang Dai

Inventor： Kefei Zhang ,  Cunming Liang ,  Ping Yu ,  Qiming Liu ,  Xingping Ruan ,  Haiyue Wang ,  Xiang Dai

IPC: G06F9/54 ,  G06F13/16

CPC classification number: G06F9/545 ,  G06F13/1663 ,  G06F2213/0026 ,  G06F2213/0038

Abstract: A processing apparatus can include a memory device having a user space for executing user applications. The processing apparatus can further include infrastructure communication circuitry that can receive a request from a user application executing in the user space. The infrastructure communication circuitry can perform a service mesh operation, in response to the request, without a sidecar proxy. Other systems and methods are described.

公开(公告)号：US20210103403A1

公开(公告)日：2021-04-08

申请号：US17092640

申请日：2020-11-09

Applicant: Shaopeng He ,  Yadong Li ,  Ziye Yang ,  Changpeng Liu ,  Haitao Kang ,  Cunming Liang ,  Gang Cao ,  Scott Peterson ,  Sujoy Sen ,  Yi Zou ,  Arun Raghunath

Inventor： Shaopeng He ,  Yadong Li ,  Ziye Yang ,  Changpeng Liu ,  Haitao Kang ,  Cunming Liang ,  Gang Cao ,  Scott Peterson ,  Sujoy Sen ,  Yi Zou ,  Arun Raghunath

IPC: G06F3/06

Abstract: Methods and apparatus for end-to-end data plane offloading for distributed storage using protocol hardware and Protocol Independent Switch Architecture (PISA) devices. Hardware-based data plane forwarding is implemented in compute and storage switches that comprise smart server switches running software executing in a kernel and user space. The compute switch is coupled to one or more compute servers/nodes and the storage server is coupled to one or more storage servers or storage arrays. The hardware-based data plane forwarding facilitates an end-to-end data plane between the computer server(s) and storage server(s)/array(s) that is offloaded to hardware. In one example the software comprises Ceph components used to implement control plane operations in connection with hardware offloaded data plane operations, and storage traffic employs the NVMe-oF protocol and the kernels include NVMe-oF modules. In one aspect the hardware-based data plane forwarding is implemented using programmable P4switch chips. In one aspect the storage and server switches are Top of Rack (ToR) switches.