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    Biasing circuit for EEPROM memories with shared latches
    1.
    发明申请
    Biasing circuit for EEPROM memories with shared latches 有权
    具有共享锁存器的EEPROM存储器的偏置电路

    公开(公告)号：US20080101125A1

    公开(公告)日：2008-05-01

    申请号：US11977876

    申请日：2007-10-26

    申请人： Antonino Conte ,  Gianbattista Logiudice ,  Giovanni Matranga ,  Mario Micciche' ,  Carmelo Ucciardello ,  Diego De Costantini

    发明人： Antonino Conte ,  Gianbattista Logiudice ,  Giovanni Matranga ,  Mario Micciche' ,  Carmelo Ucciardello ,  Diego De Costantini

    IPC分类号： G11C16/04

    CPC分类号： G11C16/12

    摘要： An EEPROM memory having a matrix of individually selectable memory cells, the matrix having a plurality of columns, a plurality of data lines each coupled with the cells of a corresponding column, the data lines being grouped in a plurality of packets, a plurality of biasing elements for providing a biasing signal to the data lines, and means for selecting the biasing elements for a selected one of the packets, wherein each biasing element is associated with corresponding data lines of a plurality of packets, the biasing element comprising switching means for selectively applying the biasing signal to a selected one of the associated data lines.

    摘要翻译： 一种EEPROM存储器，具有单独可选择的存储单元矩阵，该矩阵具有多个列，多个数据线，每条数据线与相应列的单元相耦合，数据线被分组成多个分组，多个偏置 用于向数据线提供偏置信号的元件以及用于为所选分组中的所选择的一个分组选择偏置元件的装置，其中每个偏置元件与多个分组的相应数据线相关联，所述偏置元件包括用于选择性地 将偏置信号应用到所选择的一个相关联的数据线。