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1.发明授权Method and system for automatically assigning memory modules of different predetermined capacities to contiguous segments of a linear address range 失效用于将具有不同预定容量的存储器模块自动分配给线性地址范围的连续段的方法和系统
公开(公告)号：US4908789A
公开(公告)日：1990-03-13
申请号：US034236
申请日：1987-04-01
IPC分类号： G06F12/06
CPC分类号： G06F12/0653 , G06F12/0684
摘要： A method and system for addressing memory of an information handling system in which the memory comprises a plurality of memory banks, each of which can support a plurality of different predetermined size memory modules. The sizes of the different modules are multiples of the module having the smallest size. In the embodiment described, two different sizes are employed, a 256K capacity module and a 1 Meg. capacity module, either of which can be installed in 1 of 4 memory banks. The maximum addressable address range is therefore 4 Meg. while the minimum memory is 256K. The address range can be increased in increments of 256K corresponding to 1 segment to a total of 16 contiguous segments or 4 Meg. A memory address bus comprising 22 lines is employed in the system. The 20 low order lines address each bank simultaneously. A converter converts the 4 high order address bits 22-19 to 16 sequentially ordered segment lines. A matrix of similar logic cells consisting of combinatorial logic processes each segment line to develop memory bank select signals in accordance with size signals obtained from the modules and supplied to the cells in the first row of the matrix which then provide modified size signals to remaining cells in the respective columns of the matrix. Contiguous address segments are provided from the minimum to the maximum range for every possible combination of memory modules installable in the four banks.
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公开(公告)号：US4827406A
公开(公告)日：1989-05-02
申请号：US34255
申请日：1987-04-01
CPC分类号： G06F12/0284
摘要： A plurality of processors or intelligent controllers separately utilize discrete pages of a large memory. Within each of these pages a processor can address a plurality of subdivisions or blocks utilizing the processors' address lines. Thus, separate processors having access to this memory and having a limited addressing capability can utilize a plurality of different pages of this memory, within an identical address range, and nevertheless remain confined to separate memory environments established for each of the separate processors. This is accomplished by use of a hardware register to point the separate processors to their assigned pages of the memory and a stored translate table to point to particular blocks of memory within the pages in accordance with a portion of an address generated by the processor accessing the memory.
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