公开(公告)号：US06557132B2

公开(公告)日：2003-04-29

申请号：US09791004

申请日：2001-02-22

申请人： David V. Gangl ,  Matthew Sean Grady ,  David John Iverson ,  Kenneth A. Lavallee ,  Robert Edward Shearer

发明人： David V. Gangl ,  Matthew Sean Grady ,  David John Iverson ,  Kenneth A. Lavallee ,  Robert Edward Shearer

IPC分类号： G01R3128

CPC分类号： G01R31/318342

摘要： A method for determining common failure modes of an integrated circuit device under test is disclosed. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs of the device under test. A set of output data generated by the device under test is then compared to a set of expected data, with the set of output data being generated by the device under test in response to the test pattern. It is then determined whether the set of output data has passed the test, with the set of output data passing the test if the set of output data matches the set of expected data. If the set of output data has not passed the test, then it is determined whether an output signature corresponding to the set of output data matches a previously stored output signature. Fail data corresponding to the output signature is then stored if the output signature matches a previously stored output signature.

公开(公告)号：US06754864B2

公开(公告)日：2004-06-22

申请号：US09791003

申请日：2001-02-22

申请人： David V. Gangl ,  Matthew Sean Grady ,  David John Iverson ,  Gary William Maier ,  Robert Edward Shearer ,  Donald Lawrence Wheater

发明人： David V. Gangl ,  Matthew Sean Grady ,  David John Iverson ,  Gary William Maier ,  Robert Edward Shearer ,  Donald Lawrence Wheater

IPC分类号： G01R3128

CPC分类号： G11C29/44 ,  G11C2029/5606 ,  G11C2207/104

摘要： A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether the generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.

摘要翻译： 一种用于测试嵌入式电子设备阵列的内置自检（BIST）系统和方法，所述BIST包括：移位寄存器装置，连接到被测试的电子设备的嵌入式阵列的输出引脚，并用于接收故障指示 在被测设备的实时输出引脚处的信号，移位寄存器响应于接收到故障指示而产生唯一的签名; 用于确定所生成的唯一签名是否在包含已知签名值的表中被表示的设备以及被测设备的先前确定的阵列缺陷的相应位图; 其中当确定已知的故障签名时，避免对阵列进行位图的需要。