System and method to predetermine a bitmap of a self-tested embedded array
    1.
    发明授权
    System and method to predetermine a bitmap of a self-tested embedded array 有权
    用于预先确定自测试嵌入式阵列位图的系统和方法

    公开(公告)号:US06754864B2

    公开(公告)日:2004-06-22

    申请号:US09791003

    申请日:2001-02-22

    IPC分类号: G01R3128

    摘要: A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether the generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.

    摘要翻译: 一种用于测试嵌入式电子设备阵列的内置自检(BIST)系统和方法,所述BIST包括:移位寄存器装置,连接到被测试的电子设备的嵌入式阵列的输出引脚,并用于接收故障指示 在被测设备的实时输出引脚处的信号,移位寄存器响应于接收到故障指示而产生唯一的签名; 用于确定所生成的唯一签名是否在包含已知签名值的表中被表示的设备以及被测设备的先前确定的阵列缺陷的相应位图; 其中当确定已知的故障签名时,避免对阵列进行位图的需要。

    Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability
    3.
    发明授权
    Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability 有权
    用于确定集成电路设备实现最佳可靠性所需的最小后期制作测试时间的方法和系统

    公开(公告)号:US07139944B2

    公开(公告)日:2006-11-21

    申请号:US10604887

    申请日:2003-08-25

    IPC分类号: G11C29/00 G06F11/00

    摘要: A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.

    摘要翻译: 一种用于在集成电路器件上确定最小后期制作测试时间以实现利用缺陷计数的该器件的最佳可靠性的方法和系统。 对集成电路装置上的缺陷单元或缺陷单元(DEFECTS)的有缺陷单元的数量进行计数,该计数作为确定最小测试时间的基础。 更高数量的缺陷导致更长的后期测试,以实现集成电路器件的最佳可靠性。 DEFECTS的数量可以在集成电路设备内部的设备上进行计数,并可用于确定最低要求的测试时间。 还可以通过拦截路由到另一设备的信息,在集成电路设备外部获得缺陷数量。 内部和外部提供的信息还可以显示缺陷的物理位置,以进一步完善最低要求的测试时间。