利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.013 秒)

    Streaming media encoder with front panel control interface
    1.
    发明申请
    Streaming media encoder with front panel control interface 有权
    具有前面板控制界面的流媒体编码器

    公开(公告)号：US20070055787A1

    公开(公告)日：2007-03-08

    申请号：US11220181

    申请日：2005-09-06

    申请人： Mark Hershey ,  David Stoner ,  Rick Southerland

    发明人： Mark Hershey ,  David Stoner ,  Rick Southerland

    IPC分类号： G06F15/16

    CPC分类号： H04L65/607

    摘要： A streaming media encoder for encoding and delivering media content is disclosed. The streaming media encoder has a media input interface for receiving a media stream, a media encoder for receiving the media stream from the input interface and encoding the media stream, thereby producing an encoded media stream. The media encoder has a first confidence monitor for displaying a video image from the received media stream, a second confidence monitor for displaying a video image from the encoded media stream, and a network interface for providing the encoded media stream to a network

    摘要翻译： 公开了一种用于编码和传送媒体内容的流媒体编码器。 流媒体编码器具有用于接收媒体流的媒体输入接口，用于从输入接口接收媒体流并对媒体流进行编码的媒体编码器，从而产生编码的媒体流。 媒体编码器具有用于从接收到的媒体流显示视频图像的第一置信度监视器，用于从编码媒体流显示视频图像的第二置信度监视器，以及用于将编码的媒体流提供给网络的网络接口

    Streaming media encoder with confidence monitor
    2.
    发明申请
    Streaming media encoder with confidence monitor 审中-公开
    具有置信度的流媒体编码器

    公开(公告)号：US20070053379A1

    公开(公告)日：2007-03-08

    申请号：US11220025

    申请日：2005-09-06

    申请人： Mark Hershey ,  David Stoner ,  Rick Southerland

    发明人： Mark Hershey ,  David Stoner ,  Rick Southerland

    IPC分类号： H04J3/16

    CPC分类号： H04N17/004

    摘要： A system and method for encoding an audiovisual media stream is disclosed. The method includes, receiving an input signal from an analog audiovisual source, encoding the input signal to produce an encoded media stream, providing the encoded media stream to a network interface, and displaying the received input signal on a confidence monitor.

    摘要翻译： 公开了一种用于对视听媒体流进行编码的系统和方法。 该方法包括：从模拟视听源接收输入信号，编码输入信号以产生编码的媒体流，将编码的媒体流提供给网络接口，以及在置信度监视器上显示所接收的输入信号。

    Method and apparatus for bandwidth control in an over subscribed computer network switch
    4.
    发明授权
    Method and apparatus for bandwidth control in an over subscribed computer network switch 失效
    超订购计算机网络交换机带宽控制的方法和装置

    公开(公告)号：US6145010A

    公开(公告)日：2000-11-07

    申请号：US114975

    申请日：1998-07-14

    申请人： James Scott Hiscock ,  Carl Lindeborg ,  David Stoner

    发明人： James Scott Hiscock ,  Carl Lindeborg ,  David Stoner

    IPC分类号： H04L12/56 ,  G06F13/00

    CPC分类号： H04L47/10 ,  H04L47/266 ,  H04L47/30 ,  H04L47/32 ,  H04L49/351

    摘要： A switch of a computer network with a plurality of dual speed Ethernet client ports and at least one high speed Ethernet uplink port. The combined data rate of the Ethernet dual speed client ports has a maximum value which is higher than the data rate of the Ethernet uplink port. The Bandwidth Control limits the number of enabled Ethernet client ports so that the combined data rate of the enabled client ports substantially equals, or slights exceeds the data rate of the uplink port. In this way the speed and amount of switch memory can be minimized in the switch itself and the memory burden is divided among the clients. The dividing of the memory burden greatly reduces the worst case scenario and allows each client to individually chose the speed and amount of memory based on its own cost/benefit situation.

    摘要翻译： 具有多个双速以太网客户端口和至少一个高速以太网上行链路端口的计算机网络的交换机。 以太网双速客户端端口的组合数据速率最大值高于以太网上行端口的数据速率。 带宽控制限制启用的以太网客户端端口的数量，使得启用的客户端端口的组合数据速率基本上等于，或者超过上行链路端口的数据速率。 以这种方式，开关本身的开关存储器的速度和数量可以最小化，并且存储器负担在客户端之间分配。 内存负担的划分大大降低了最坏情况，允许每个客户端根据自身的成本/效益情况单独选择内存的速度和数量。

    LAN to ATM backbone switch module
    5.
    发明授权
    LAN to ATM backbone switch module 失效
    LAN到ATM主干交换机模块

    公开(公告)号：US6052383A

    公开(公告)日：2000-04-18

    申请号：US865242

    申请日：1997-05-29

    申请人： David Stoner ,  Carl John Lindeborg ,  Norm Magnan

    发明人： David Stoner ,  Carl John Lindeborg ,  Norm Magnan

    IPC分类号： H04L12/46 ,  H04L12/56 ,  H04Q11/04 ,  H04T3/16 ,  H04L12/28

    CPC分类号： H04L49/309 ,  H04L12/4608 ,  H04Q11/0478 ,  H04L2012/5618 ,  H04L2012/5665

    摘要： A LAN to ATM switch module includes a memory with an ATM port, a LAN port and a processor port. Each of port separately reading and writing information to/from the memory. An ATM interface is included for reading information from the ATM port and converting the information into an ATM format. The ATM interface also converts ATM format information to be delivered to the ATM port and written to the memory. A LAN interface reads information from the LAN port and converts the information into LAN format. The LAN interface also converts LAN information from a LAN packet channel bus to the LAN port, to be written to the memory. The switch module also includes a processor for reading information in the memory through the processor port. The processor determines the processing need for the information, the processor modifies the information in the memory according to the processing needed by writing to the memory through the processor port and controlling the ATM and LAN interfaces according to the processing needed.

    摘要翻译： LAN到ATM交换机模块包括具有ATM端口，LAN端口和处理器端口的存储器。 每个端口分别读取和写入信息到内存。 ATM接口包括用于从ATM端口读取信息并将信息转换成ATM格式。 ATM接口还将要传送到ATM端口的ATM格式信息转换并写入存储器。 LAN接口从LAN端口读取信息，并将信息转换为LAN格式。 LAN接口还将LAN信息从LAN分组信道总线转换为LAN端口，以将其写入存储器。 交换模块还包括一个处理器，用于通过处理器端口读取存储器中的信息。 处理器确定对信息的处理需求，处理器根据通过处理器端口写入存储器所需的处理来修改存储器中的信息，并根据所需的处理来控制ATM和LAN接口。

    Multiported memory access system with arbitration and a source burst limiter for blocking a memory access request
    6.
    发明授权
    Multiported memory access system with arbitration and a source burst limiter for blocking a memory access request 失效
    具有仲裁的多端口存储器访问系统和用于阻塞存储器访问请求的源突发限制器

    公开(公告)号：US6032232A

    公开(公告)日：2000-02-29

    申请号：US865243

    申请日：1997-05-29

    申请人： Carl John Lindeborg ,  David Stoner

    发明人： Carl John Lindeborg ,  David Stoner

    IPC分类号： G06F13/18 ,  G06F12/00 ,  G06F13/28

    CPC分类号： G06F13/18

    摘要： A multiport or multiported memory device is provided. A first user and at least a second user are provided. A multilevel memory arbitration system is implemented which establishes arbitration cycles wherein the high priority user is granted priority as to access either during each arbitration cycle or during a greater number of arbitration cycles. A source burst limiter is provided associated with the high priority user. The source burst limiter monitors access of the high priority user to the multiport memory and limits such access based on a comparison of access attributes to some access attribute threshold.

    摘要翻译： 提供多端口或多端口存储器件。 提供第一用户和至少第二用户。 实施多级存储器仲裁系统，其建立仲裁周期，其中高优先级用户被授予在每个仲裁周期期间或在更大数量的仲裁周期期间访问的优先级。 提供与高优先级用户相关联的源突发限制器。 源突发限制器监视高优先级用户对多端口存储器的访问，并且基于访问属性与某些访问属性阈值的比较来限制这种访问。