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公开(公告)号：US07018095B2
公开(公告)日：2006-03-28
申请号：US10184534
申请日：2002-06-27
CPC分类号： G01K7/01
摘要： A circuit for sensing on-die temperature at multiple locations using a minimum number of pins is described. Thermal diodes coupled to pins are placed on a die to measure the temperature at various die locations. Voltage is applied to the pins to determine the temperature at each given diode location. The polarity of the voltage applied across the pins determines what diodes are selected for measurement.
摘要翻译： 描述了一种用于使用最少数量的引脚来感测多个位置处的片上温度的电路。 耦合到引脚的热二极管放置在管芯上以测量各个管芯位置处的温度。 电压施加到引脚以确定每个给定二极管位置处的温度。 引脚上施加的电压极性决定了哪些二极管用于测量。
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2.发明授权Method and apparatus to measure statistical variation of electrical signal phase in integrated circuits using time-correlated photon counting 失效使用时间相关光子计数来测量集成电路中电信号相位的统计变化的方法和装置公开(公告)号：US06596980B2
公开(公告)日：2003-07-22
申请号：US09944240
申请日：2001-08-31
IPC分类号： H01L3100
CPC分类号： G01R31/31709 , G01R31/311
摘要： Time-correlated photon counting is used to measure integrated circuit (IC) performance related to signal jitter (such as clock jitter) in a manner that is non-invasive to the circuit or node of interest. The signal jitter is measured by counting photon emissions at various nodes of interest across a controlled collapse chip connect (C4) mounted die, without interfering with the normal operation of the circuit of interest. This increases the precision and accuracy of the measurement of signal jitter significantly, since small amounts of phase noise on a particular clock signal edge can be detected. The emitted photons can be detected and subsequently correlated to a precise time base to obtain a statistical spread of switching events in time. The range of the photon distribution can be used to reliably determine safe and reasonable timing guard bands for clock and data paths in an IC.
摘要翻译： 时间相关光子计数用于以对感兴趣的电路或节点无创的方式测量与信号抖动（例如时钟抖动）相关的集成电路（IC）性能。 通过在受控的崩溃芯片连接（C4）安装的管芯上计算感兴趣的各个节点处的光子发射来测量信号抖动，而不干扰感兴趣的电路的正常操作。 这可以显着提高信号抖动测量的精度和精度，因为可以检测到特定时钟信号边沿上的少量相位噪声。 发射的光子可以被检测并随后与精确的时基相关联，以及时获得切换事件的统计扩展。 光子分布的范围可用于可靠地确定IC中时钟和数据路径的安全合理的定时保护带。
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公开(公告)号：US06519744B2
公开(公告)日：2003-02-11
申请号：US09735742
申请日：2000-12-12
IPC分类号： G06F1750
CPC分类号： G01R31/311
摘要： A method is provided for manufacturing a die. A supply voltage is provided to a power plane of a selected integrated circuit, formed in and on a semiconductor substrate, having a selected design, so that a respective test current flows through a plurality of test elements, of the selected integrated circuit, each being connected to a respective test point on the power plane, the test points being spaced from one another. A magnitude of each respective test current is detected. A respective test voltage is calculated at each respective test point utilizing the respective magnitude of the respective test current flowing through the respective test element connected to a respective test point. The respective test voltages are utilized to determine at which ones of the test points the respective test voltages are more than a predetermined maximum below a supply voltage. The electric design is altered to an altered electric design if any of the test voltages are below a predetermined minimum below the supply voltage. An integrated circuit having the altered design is then manufactured on another semiconductor substrate.
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