公开(公告)号：US20110185208A1

公开(公告)日：2011-07-28

申请号：US12895702

申请日：2010-09-30

申请人： Derek Iwamoto ,  Steven J. Sfarzo ,  Ryan Schmidt ,  Derrick Carty ,  Keith Cox

发明人： Derek Iwamoto ,  Steven J. Sfarzo ,  Ryan Schmidt ,  Derrick Carty ,  Keith Cox

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G11C5/141 ,  G11C5/148 ,  G11C11/4074 ,  Y02D10/14 ,  Y02D50/20

摘要： A data processing system that uses memory power reduction in a sleep state. The system can include a volatile memory and at least one data input peripheral and a logic circuit that is configured to manage power consumption of the data processing system for a sleep of the system. The logic circuit can be coupled to the volatile memory and can be configured to turn off power to the volatile memory in response to an event, occurring during the sleep state, but to otherwise remain in the sleep state. The sleep state can be an ACPI complaint S3 sleep state in which the volatile memory, such as DRAM, is powered off after a period of user inactivity during the S3 sleep state.

摘要翻译： 在休眠状态下使用存储器功率降低的数据处理系统。 该系统可以包括易失性存储器和至少一个数据输入外围设备和逻辑电路，该逻辑电路被配置为管理数据处理系统对系统的睡眠的功耗。 逻辑电路可以耦合到易失性存储器，并且可以被配置为响应于在睡眠状态期间发生的事件而关闭到易失性存储器的电力，但是否则保持在睡眠状态。 休眠状态可以是ACMI投诉S3休眠状态，其中诸如DRAM之类的易失性存储器在S3睡眠状态期间的用户不活动期间之后被关闭。