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公开(公告)号：US4924484A
公开(公告)日：1990-05-08
申请号：US263092
申请日：1988-10-27
CPC分类号： H03K3/0372 , H03K23/50
摘要： A high speed counter circuit for counting electrical pulses includes a master/slave flip-flop at the input stage of the counter. An AND gate logically ANDs the pulses being counted with the master output to produce a first gating signal. A plurality of cascade coupled flip-flops each having a slave and an inverse slave output are provided. The clock input to each cascade coupled flip-flop is produced by the logical OR of the electrical pulses being counted, the first gating signal and the slave output of all preceding flip-flops of the counter. The counter output is provided by the inverse slave output of each flip-flop.
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2.发明授权Programmable delay line utilizing measured actual delays to provide a highly accurate delay 失效可编程延迟线利用测量的实际延迟提供高精度的延迟
公开(公告)号：US5013944A
公开(公告)日：1991-05-07
申请号：US340999
申请日：1989-04-20
申请人： Jeffrey H. Fischer , Lawrence J. Grasso , Dale E. Hoffman , Daniel E. Skooglund , Diane K. Young
发明人： Jeffrey H. Fischer , Lawrence J. Grasso , Dale E. Hoffman , Daniel E. Skooglund , Diane K. Young
CPC分类号： H03K5/131 , H03K5/135 , H03K2005/00097 , H03K2005/00104 , H03K2005/00247 , H03K2005/00254
摘要： A method of operating a delay circuit to impose a selected delay on an electronic signal the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method comprising the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.
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