利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

179 条记录 (耗时 0.026 秒)

    Memory package, semiconductor device, and storage device
    1.
    发明授权
    Memory package, semiconductor device, and storage device 有权

    公开(公告)号：US11736098B2

    公开(公告)日：2023-08-22

    申请号：US17866517

    申请日：2022-07-17

    申请人： Samsung Electronics Co., Ltd.

    发明人： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon ,  Byungkwan Chun ,  Byunghoon Jeong

    IPC分类号： H03K5/14 ,  H03L7/081 ,  H03K5/135 ,  H03K5/00

    CPC分类号： H03K5/14 ,  H03K5/135 ,  H03L7/0816 ,  H03K2005/00247

    摘要： A memory package includes a plurality of memory chips, and an interface chip relaying communications between a controller and the plurality of memory chips and receiving a plurality of signals from the plurality of memory chips. The interface chip includes receivers outputting a data signal and a raw clock signal based on the plurality of signals, a delay circuit outputting a delay clock signal by applying an offset delay corresponding to ½ of one unit interval of the data signal and an additional delay to the raw clock signal, and a sampler sampling the data signal in synchronization with a clock signal. The delay circuit outputs the clock signal generated by removing the offset delay from the delay clock signal when the delay clock signal and the data signal have a phase difference corresponding to one unit interval of the data signal.

    Delay structure for a memory interface
    6.
    发明授权
    Delay structure for a memory interface 有权
    存储器接口的延迟结构

    公开(公告)号：US09520864B2

    公开(公告)日：2016-12-13

    申请号：US14298742

    申请日：2014-06-06

    申请人： QUALCOMM Incorporated

    发明人： Jan Christian Diffenderfer ,  Yuehchun Claire Cheng

    IPC分类号： H03K5/13 ,  G11C7/10 ,  H03K5/135 ,  H03K5/00

    CPC分类号： H03K5/13 ,  G11C7/1072 ,  H03K5/131 ,  H03K5/135 ,  H03K2005/00026 ,  H03K2005/00247 ,  H03K2005/00286

    摘要： Systems and methods for delaying a signal are described herein. In one embodiment, a method for delaying a signal comprises receiving a first signal edge, and, in response to receiving the first signal edge, counting a number of oscillations of an oscillator. The method also comprises outputting a second signal edge if the number of oscillations reaches a predetermined number. The second signal edge represents a delayed version of the first signal edge.

    摘要翻译： 本文描述了用于延迟信号的系统和方法。 在一个实施例中，一种用于延迟信号的方法包括接收第一信号边缘，并且响应于接收到第一信号边沿，对振荡器的振荡次数进行计数。 该方法还包括如果振荡次数达到预定数量则输出第二信号沿。 第二信号边缘表示第一信号边沿的延迟版本。

    Tunable clock system
    7.
    发明授权
    Tunable clock system 有权
    可调时钟系统

    公开(公告)号：US09124256B2

    公开(公告)日：2015-09-01

    申请号：US14589444

    申请日：2015-01-05

    申请人： Laurence H. Cooke

    发明人： Laurence H. Cooke

    IPC分类号： H03K3/00 ,  H03K5/13 ,  H03K5/00

    CPC分类号： H03K5/15 ,  H03K5/131 ,  H03K5/133 ,  H03K5/15013 ,  H03K2005/00065 ,  H03K2005/00247

    摘要： A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

    摘要翻译： 由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中 可能是因为例如深亚微米器件和互连中的物理变化。 还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。 还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。

    TUNABLE CLOCK SYSTEM
    8.
    发明申请
    TUNABLE CLOCK SYSTEM 审中-公开
    时钟系统

    公开(公告)号：US20150109039A1

    公开(公告)日：2015-04-23

    申请号：US14589444

    申请日：2015-01-05

    申请人： Laurence H. COOKE

    发明人： Laurence H. COOKE

    IPC分类号： H03K5/13

    CPC分类号： H03K5/15 ,  H03K5/131 ,  H03K5/133 ,  H03K5/15013 ,  H03K2005/00065 ,  H03K2005/00247

    摘要： A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

    摘要翻译： 由可变电阻器元件组成的存储器状结构，用于调整时钟分配结构的相应分支和叶片，其可用于补偿逐芯片和/或组合逻辑逐个路径延迟变化，其中 可能是因为例如深亚微米器件和互连中的物理变化。 还提供了具有执行延迟测试测量功能的单个系统时钟扫描触发器。 还提出了用于测量组合逻辑路径延迟以确定最大时钟频率和编程可变电阻器的延迟的方法，以及用于校准和测量编程的可变电阻器的方法。

    Method and System for Providing a Power-On Reset Pulse
    10.
    发明申请
    Method and System for Providing a Power-On Reset Pulse 有权
    提供上电复位脉冲的方法和系统

    公开(公告)号：US20090167378A1

    公开(公告)日：2009-07-02

    申请号：US12400567

    申请日：2009-03-09

    申请人： Alireza Zolfaghari

    发明人： Alireza Zolfaghari

    IPC分类号： H03L7/00

    CPC分类号： H03K17/22 ,  H03K2005/00247

    摘要： Provided are a method and system for providing a power-on reset pulse. The system includes a level detector configured to receive an input signal and produce, at least indirectly, a reset signal when the input signal reaches a predetermined level. The system also includes a counter having counting characteristics and configured to receive the reset signal and a clock signal. The counter produces a delayed signal in accordance with the counting characteristics, the clock signal, and the received reset signal.

    摘要翻译： 提供一种用于提供上电复位脉冲的方法和系统。 该系统包括电平检测器，其被配置为当输入信号达到预定电平时接收输入信号并产生至少间接的复位信号。 该系统还包括具有计数特性并被配置为接收复位信号和时钟信号的计数器。 计数器根据计数特性，时钟信号和接收到的复位信号产生延迟信号。