Asymmetric multilayered dielectric material and a flash EEPROM using the
same
    1.
    发明授权
    Asymmetric multilayered dielectric material and a flash EEPROM using the same 失效
    非对称多层电介质材料和使用其的闪存EEPROM

    公开(公告)号:US5331189A

    公开(公告)日:1994-07-19

    申请号:US901281

    申请日:1992-06-19

    摘要: A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate to the floating gate and by tunneling from the floating gate to the erase gate, respectively. The directional dielectric employed is a multilayered structured (MLS) oxide, where thin oxide and thin polycrystalline silicon form alternating layers. The layering is asymmetric: that is, either the uppermost or bottommost layer is thicker than the other layers. As a result of this structure, the oxide exhibits directionality, that is, the tunneling is easier in one direction than the reverse direction, and significantly enhances the tunneling phenomena (tunneling current can be observed at as low as 4.7 V). In addition, the MLS oxide can be fabricated having different dielectric constants. The directionality, coupled with the separate write and erase gates, gives the new flash EEPROM cell a number of advantages: it is low-voltage operable, it is highly resistant to disturbance and has an easily scalable structure (that is, it can be made to operate at any given voltage within a specified scale).

    摘要翻译: 制造包括多个MOS单元的快闪EEPROM。 在每个单元中,通过从写入栅极到浮动栅极的隧穿以及分别从浮置栅极到擦除栅极的隧穿来执行编程和擦除。 所采用的定向电介质是多层结构(MLS)氧化物,其中薄的氧化物和薄的多晶硅形成交替层。 分层是不对称的,也就是说,最上层或最底层比其他层厚。 作为该结构的结果,氧化物具有方向性,即,在一个方向上的隧道比反向更容易,并且显着增强了隧道现象(隧道电流可以在低至4.7V)。 此外,可以制造具有不同介电常数的MLS氧化物。 方向性与单独的写入和擦除门相结合,为新的快闪EEPROM单元提供了许多优点:它是低电压可操作的,它具有高度的抗干扰性,并且具有易于扩展的结构(即可以制成 在指定电压范围内工作)。

    Method for manufacturing a memory cell
    2.
    发明授权
    Method for manufacturing a memory cell 失效
    存储单元的制造方法

    公开(公告)号:US5451535A

    公开(公告)日:1995-09-19

    申请号:US247170

    申请日:1994-05-20

    摘要: A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate to the floating gate and by tunneling from the floating gate to the erase gate, respectively. The directional dielectric employed is a multilayered structured (MLS) oxide, where thin oxide and thin polycrystalline silicon form alternating layers. The layering is asymmetric: that is, either the uppermost or bottommost layer is thicker than the other layers. As a result of this structure, the oxide exhibits directionality, that is, the tunneling is easier in one direction than the reverse direction, and significantly enhances the tunneling phenomena (tunneling current can be observed at as low as 4.7 V). In addition, the MLS oxide can be fabricated having different dielectric constants. The directionality, coupled with the separate write and erase gates, gives the new flash EEPROM cell a number of advantages: it is low-voltage operable, it is highly resistant to disturbance and has an easily scalable structure (that is, it can be made to operate at any given voltage within a specified scale).

    摘要翻译: 制造包括多个MOS单元的快闪EEPROM。 在每个单元中,通过从写入栅极到浮动栅极的隧穿以及分别从浮置栅极到擦除栅极的隧穿来执行编程和擦除。 所采用的定向电介质是多层结构(MLS)氧化物,其中薄的氧化物和薄的多晶硅形成交替层。 分层是不对称的,也就是说,最上层或最底层比其他层厚。 作为该结构的结果,氧化物具有方向性,即,在一个方向上的隧道比反向更容易,并且显着增强了隧道现象(隧道电流可以在低至4.7V)。 此外,可以制造具有不同介电常数的MLS氧化物。 方向性与单独的写入和擦除门相结合,为新的快闪EEPROM单元提供了许多优点:它是低电压可操作的,它具有高度的抗干扰性,并且具有易于扩展的结构(即可以制成 在指定电压范围内工作)。