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1.发明授权Semiconductor on insulator (SOI) device including a discharge path for a decoupling capacitor 有权具有用于去耦电容器的放电路径的半导体绝缘体（SOI）器件公开(公告)号：US07915658B2
公开(公告)日：2011-03-29
申请号：US12727027
申请日：2010-03-18
IPC分类号： H01L27/108
CPC分类号： H01L27/0255 , H01L21/743 , H01L21/84 , H01L27/1203
摘要： A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
摘要翻译： 提供了一种绝缘体上硅（SOI）器件。 该器件包括耦合在电压总线之间并形成在覆盖绝缘体层和半导体衬底的单晶半导体层中的MOS电容器。 该器件包括至少一个放电路径，用于在MOS电容器上放出潜在的有害电荷。 MOS电容器具有形成MOS电容器的第一板的导电电极材料和形成第二板的导电电极材料下面的单晶硅层中的杂质掺杂区域。 第一电压总线耦合到电容器的第一板和通过形成在半导体衬底中的二极管的放电路径，第二电压总线耦合到电容器的第二板。
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公开(公告)号：US20100187586A1
公开(公告)日：2010-07-29
申请号：US12727027
申请日：2010-03-18
IPC分类号： H01L27/12
CPC分类号： H01L27/0255 , H01L21/743 , H01L21/84 , H01L27/1203
摘要： A silicon on insulator (SOI) device is provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
摘要翻译： 提供了一种绝缘体上硅（SOI）器件。 该器件包括耦合在电压总线之间并形成在覆盖绝缘体层和半导体衬底的单晶半导体层中的MOS电容器。 该器件包括至少一个放电路径，用于在MOS电容器上放出潜在的有害电荷。 MOS电容器具有形成MOS电容器的第一板的导电电极材料和形成第二板的导电电极材料下面的单晶硅层中的杂质掺杂区域。 第一电压总线耦合到电容器的第一板和通过形成在半导体衬底中的二极管的放电路径，第二电压总线耦合到电容器的第二板。
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公开(公告)号：US07718503B2
公开(公告)日：2010-05-18
申请号：US11459316
申请日：2006-07-21
IPC分类号： H01L21/20
CPC分类号： H01L27/0255 , H01L21/743 , H01L21/84 , H01L27/1203
摘要： A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
摘要翻译： 提供一种绝缘体上硅（SOI）器件及其制造方法。 该器件包括耦合在电压总线之间并形成在覆盖绝缘体层和半导体衬底的单晶半导体层中的MOS电容器。 该器件包括至少一个放电路径，用于在MOS电容器上放出潜在的有害电荷。 MOS电容器具有形成MOS电容器的第一板的导电电极材料和形成第二板的导电电极材料下面的单晶硅层中的杂质掺杂区域。 第一电压总线耦合到电容器的第一板和通过形成在半导体衬底中的二极管的放电路径，第二电压总线耦合到电容器的第二板。
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公开(公告)号：US20080017906A1
公开(公告)日：2008-01-24
申请号：US11459316
申请日：2006-07-21
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L27/0255 , H01L21/743 , H01L21/84 , H01L27/1203
摘要： A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.
摘要翻译： 提供一种绝缘体上硅（SOI）器件及其制造方法。 该器件包括耦合在电压总线之间并形成在覆盖绝缘体层和半导体衬底的单晶半导体层中的MOS电容器。 该器件包括至少一个放电路径，用于在MOS电容器上放出潜在的有害电荷。 MOS电容器具有形成MOS电容器的第一板的导电电极材料和形成第二板的导电电极材料下面的单晶硅层中的杂质掺杂区域。 第一电压总线耦合到电容器的第一板和通过形成在半导体衬底中的二极管的放电路径，第二电压总线耦合到电容器的第二板。
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