公开(公告)号：US08546855B2

公开(公告)日：2013-10-01

申请号：US13239865

申请日：2011-09-22

申请人： Jingrong Zhou ,  David Wu ,  James F. Buller

发明人： Jingrong Zhou ,  David Wu ,  James F. Buller

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/0255 ,  H01L21/84 ,  H01L27/1203

摘要： Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a P+ substrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P+-doped substrate contact in the bulk silicon layer of the SOI substrate.

摘要翻译： 形成具有改进的电荷保护的浅沟槽隔离绝缘体上硅（SOI）器件。 实施例包括作为充电保护装置的SOI膜二极管和P +衬底结。 实施例还包括从SOI晶体管漏极，通过导电触点，金属线，第二导电触点，与晶体管隔离的SOI二极管，第三导电触点，第二导线和第四导电触点的导电路径 到SOI衬底的体硅层中的P +掺杂的衬底接触。

公开(公告)号：US08076703B2

公开(公告)日：2011-12-13

申请号：US12603353

申请日：2009-10-21

申请人： Akif Sultan ,  James F. Buller ,  Kaveri Mathur

发明人： Akif Sultan ,  James F. Buller ,  Kaveri Mathur

IPC分类号： H01L29/78

CPC分类号： H01L27/1203 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/7843

摘要： A semiconductor device is provided which includes a substrate including an inactive region and an active region, a gate electrode structure having portions overlying the active region, a compressive layer overlying the active region, and a tensile layer overlying the inactive region and located outside the active region. The active region has a lateral edge which defines a width of the active region, and a transverse edge which defines a length of the active region. The gate electrode structure includes: a common portion spaced apart from the active region; a plurality of gate electrode finger portions integral with the common portion, and a plurality of fillet portions integral with the common portion and the gate electrode finger portions. A portion of each gate electrode finger portion overlies the active region. The fillet portions are disposed between the common portion and the gate electrode finger portions, and do not overlie the active region. The compressive layer also overlies the gate electrode finger portions, and the tensile layer is disposed adjacent the transverse edge of the active region.

摘要翻译： 提供了一种半导体器件，其包括：基板，其包括非活性区域和有源区域;栅极电极结构，其具有覆盖有源区域的部分;覆盖有源区域的压缩层;以及覆盖非活性区域并位于有源区域外部的拉伸层 地区。 有源区域具有限定有源区域的宽度的横向边缘和限定有源区域的长度的横向边缘。 栅电极结构包括：与有源区间隔开的公共部分; 与公共部分成一体的多个栅极电极指部，以及与公共部分和栅电极指部分成一体的多个圆角部分。 每个栅电极指部分的一部分覆盖有源区。 圆角部分设置在公共部分和栅极电极指部分之间，并且不覆盖有源区域。 压电层也覆盖在栅极电极指部分上，并且拉伸层邻近有源区的横向边缘设置。

公开(公告)号：US07718503B2

公开(公告)日：2010-05-18

申请号：US11459316

申请日：2006-07-21

申请人： Mario M. Pellela ,  Donggang D. Wu ,  James F. Buller

发明人： Mario M. Pellela ,  Donggang D. Wu ,  James F. Buller

IPC分类号： H01L21/20

CPC分类号： H01L27/0255 ,  H01L21/743 ,  H01L21/84 ,  H01L27/1203

摘要： A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

摘要翻译： 提供一种绝缘体上硅（SOI）器件及其制造方法。 该器件包括耦合在电压总线之间并形成在覆盖绝缘体层和半导体衬底的单晶半导体层中的MOS电容器。 该器件包括至少一个放电路径，用于在MOS电容器上放出潜在的有害电荷。 MOS电容器具有形成MOS电容器的第一板的导电电极材料和形成第二板的导电电极材料下面的单晶硅层中的杂质掺杂区域。 第一电压总线耦合到电容器的第一板和通过形成在半导体衬底中的二极管的放电路径，第二电压总线耦合到电容器的第二板。

公开(公告)号：US20090081860A1

公开(公告)日：2009-03-26

申请号：US11861534

申请日：2007-09-26

申请人： Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

发明人： Jingrong ZHOU ,  Mark MICHAEL ,  Donna Michael ,  David WU ,  James F. BULLER ,  Akif SULTAN

IPC分类号： H01L21/425

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/1083

摘要： The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

摘要翻译： 本文描述的光晕植入技术采用在光晕掺杂剂轰击期间产生晕轮植入物阴影效应的光晕注入掩模。 第一晶体管器件结构和第二晶体管器件结构形成在晶片上，使得它们彼此正交地取向。 创建了常见的光晕注入掩模，其特征在于，在第一晶体管器件结构的扩散区域的晕圈注入期间防止第二晶体管器件结构的扩散区域的光晕注入，并且具有防止第 在第二晶体管器件结构的扩散区的晕圈注入期间的第一晶体管器件结构。 晶体管器件结构的正交取向和光晕注入掩模的图案消除了创建多个注入掩模以实现晶体管器件结构的不同阈值电压的需要。

公开(公告)号：US20080296682A1

公开(公告)日：2008-12-04

申请号：US11755930

申请日：2007-05-31

申请人： Jianhong ZHU ,  Jinrong ZHOU ,  David WU ,  James F. BULLER

发明人： Jianhong ZHU ,  Jinrong ZHOU ,  David WU ,  James F. BULLER

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L21/84 ,  H01L21/76895 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/1203 ,  H01L29/7843

摘要： MOS structures with remote contacts and methods for fabricating such MOS structures are provided. In one embodiment, a method for fabricating an MOS structure comprises providing a semiconductor layer that is at least partially surrounded by an isolation region and that has an impurity-doped first portion. First and second MOS transistors are formed on and within the first portion. The transistors are substantially parallel and define a space therebetween. An insulating material is deposited overlying the first portion of the semiconductor layer and at least a portion of the isolation region. A contact is formed through the insulating material outside the space such that the contact is in electrical communication with the transistors.

摘要翻译： 提供了具有远程触点的MOS结构和用于制造这种MOS结构的方法。 在一个实施例中，一种用于制造MOS结构的方法包括提供半导体层，该半导体层至少部分地被隔离区包围，并且具有杂质掺杂的第一部分。 第一和第二MOS晶体管形成在第一部分内部和第一部分内。 晶体管基本上平行并且在它们之间限定了一个空间。 沉积覆盖半导体层的第一部分和隔离区域的至少一部分的绝缘材料。 通过空间外部的绝缘材料形成触点，使得触点与晶体管电连通。

公开(公告)号：US07417250B1

公开(公告)日：2008-08-26

申请号：US11151550

申请日：2005-06-14

申请人： James F. Buller ,  Derick J Wristers ,  Qi Xiang ,  Bin Yu

发明人： James F. Buller ,  Derick J Wristers ,  Qi Xiang ,  Bin Yu

IPC分类号： H01L29/04

CPC分类号： H01L21/823807 ,  H01L29/1054

摘要： A method of manufacturing a semiconductor device includes providing a strained-silicon semiconductor layer over a silicon germanium layer, and partially removing a first portion of the strained-silicon layer. The strained-silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the strained-silicon layer initially can have the same thickness. A p-channel transistor is formed over the first portion, and a n-channel transistor is formed over the second portion. A semiconductor device is also disclosed.

摘要翻译： 制造半导体器件的方法包括在硅锗层上提供应变硅半导体层，并部分去除应变硅层的第一部分。 应变硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。 最初，应变硅层的第一和第二部分最初可以具有相同的厚度。 在第一部分上形成p沟道晶体管，并且在第二部分上形成n沟道晶体管。 还公开了一种半导体器件。

公开(公告)号：US20080017906A1

公开(公告)日：2008-01-24

申请号：US11459316

申请日：2006-07-21

申请人： Mario M. Pelella ,  Donggang D. Wu ,  James F. Buller

发明人： Mario M. Pelella ,  Donggang D. Wu ,  James F. Buller

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L27/0255 ,  H01L21/743 ,  H01L21/84 ,  H01L27/1203

摘要： A silicon on insulator (SOI) device and methods for fabricating such a device are provided. The device includes an MOS capacitor coupled between voltage busses and formed in a monocrystalline semiconductor layer overlying an insulator layer and a semiconductor substrate. The device includes at least one electrical discharge path for discharging potentially harmful charge build up on the MOS capacitor. The MOS capacitor has a conductive electrode material forming a first plate of the MOS capacitor and an impurity doped region in the monocrystalline silicon layer beneath the conductive electrode material forming a second plate. A first voltage bus is coupled to the first plate of the capacitor and to an electrical discharge path through a diode formed in the semiconductor substrate and a second voltage bus is coupled to the second plate of the capacitor.

摘要翻译： 提供一种绝缘体上硅（SOI）器件及其制造方法。 该器件包括耦合在电压总线之间并形成在覆盖绝缘体层和半导体衬底的单晶半导体层中的MOS电容器。 该器件包括至少一个放电路径，用于在MOS电容器上放出潜在的有害电荷。 MOS电容器具有形成MOS电容器的第一板的导电电极材料和形成第二板的导电电极材料下面的单晶硅层中的杂质掺杂区域。 第一电压总线耦合到电容器的第一板和通过形成在半导体衬底中的二极管的放电路径，第二电压总线耦合到电容器的第二板。

公开(公告)号：US6037224A

公开(公告)日：2000-03-14

申请号：US850853

申请日：1997-05-02

申请人： James F. Buller ,  H. Jim Fulford, Jr.

发明人： James F. Buller ,  H. Jim Fulford, Jr.

IPC分类号： H01L21/8234 ,  H01L21/8247

CPC分类号： H01L21/823462

摘要： A method for growing dual thickness oxide includes the step of forming a first oxide having a first thickness. A thin layer of the first oxide is transformed into an oxygen diffusion barrier, wherein the oxygen diffusion barrier interfaces at the silicon substrate. A portion of the oxide and oxygen diffusion barrier is removed to expose an area on the silicon substrates. Thereafter, a second oxide is formed on the exposed area of the silicon substrate surface wherein the second silicon dioxide has a second thickness different from the first thickness.

摘要翻译： 生长双重厚度氧化物的方法包括形成具有第一厚度的第一氧化物的步骤。 第一氧化物的薄层转变成氧扩散阻挡层，其中氧扩散阻挡层在硅衬底处相互接触。 去除一部分氧化物和氧扩散阻挡层以露出硅衬底上的区域。 此后，在硅衬底表面的暴露区域上形成第二氧化物，其中第二二氧化硅具有不同于第一厚度的第二厚度。

公开(公告)号：US08183107B2

公开(公告)日：2012-05-22

申请号：US12473074

申请日：2009-05-27

申请人： Kaveri Mathur ,  James F. Buller ,  Andreas Kurz

发明人： Kaveri Mathur ,  James F. Buller ,  Andreas Kurz

IPC分类号： H01L21/8232

CPC分类号： H01L29/8605 ,  H01L27/0738 ,  H01L27/0802 ,  H01L29/66166

摘要： Semiconductor devices are formed with reduced variability between close proximity resistors, improved end resistances, and reduced random dopant mismatch. Embodiments include ion implanting a dopant, such as B, at a relatively high dosage, e.g. about 4 to about 6 keV, and at a relatively low implant energy, e.g., about 1.5 to about 2E15/cm2.

摘要翻译： 半导体器件形成在近距离电阻之间具有降低的变异性，改善的端电阻和减少的随机掺杂物失配。 实施例包括以相当高的剂量例如离子注入掺杂剂，例如B。 约4至约6keV，并且在相对较低的注入能量下，例如约1.5至约2E15 / cm 2。

公开(公告)号：US08089125B2

公开(公告)日：2012-01-03

申请号：US11759454

申请日：2007-06-07

申请人： Jianhong Zhu ,  Ruigang Li ,  James F. Buller ,  David Wu

发明人： Jianhong Zhu ,  Ruigang Li ,  James F. Buller ,  David Wu

IPC分类号： H01L27/12

CPC分类号： H01L21/84 ,  H01L27/0617 ,  H01L27/0817 ,  H01L27/1203

摘要： An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit.

摘要翻译： 集成电路系统包括集成电路，在集成电路附近形成三极管，并将连接器连接到三极管和集成电路。