公开(公告)号：US20100202220A1

公开(公告)日：2010-08-12

申请号：US12692512

申请日：2010-01-22

申请人： Kuoyuan Peter HSU ,  TaeHyung Jung ,  Douk Hyoun Ryu ,  Young Suk Kim

发明人： Kuoyuan Peter HSU ,  TaeHyung Jung ,  Douk Hyoun Ryu ,  Young Suk Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/4076

摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.

摘要翻译： 存储电路包括至少一个用于存储表示数据的电荷的存储单元。 存储单元与字线和第一位线耦合。 至少一个位线均衡晶体管耦合在第一位线和第二位线之间。 位线均衡电路与位线均衡晶体管耦合。 位线均衡电路被配置为向位线均衡晶体管提供脉冲，以在存储单元的访问周期之前的待机期间基本上均衡第一位线和第二位线的电压。

公开(公告)号：US08279686B2

公开(公告)日：2012-10-02

申请号：US12692512

申请日：2010-01-22

申请人： Kuoyuan Peter Hsu ,  TaeHyung Jung ,  Douk Hyoun Ryu ,  Young Suk Kim

发明人： Kuoyuan Peter Hsu ,  TaeHyung Jung ,  Douk Hyoun Ryu ,  Young Suk Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/4076

摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.

摘要翻译： 存储电路包括至少一个用于存储表示数据的电荷的存储单元。 存储单元与字线和第一位线耦合。 至少一个位线均衡晶体管耦合在第一位线和第二位线之间。 位线均衡电路与位线均衡晶体管耦合。 位线均衡电路被配置为向位线均衡晶体管提供脉冲，以在存储单元的访问周期之前的待机期间基本上均衡第一位线和第二位线的电压。

公开(公告)号：US5946225A

公开(公告)日：1999-08-31

申请号：US75049

申请日：1998-05-08

申请人： Douk Hyoun Ryu ,  Yong Chul Cho ,  In Hwan Eum

发明人： Douk Hyoun Ryu ,  Yong Chul Cho ,  In Hwan Eum

IPC分类号： G11C11/413 ,  G11C11/412 ,  G11C11/00

CPC分类号： G11C11/4125

摘要： A SRAM device according to the present invention performs a stable data latch operation. The present invention provides a negative voltage generator which is coupled to the drive transistors in the SRAM device for providing negative voltage for the drive transistors during a read cycle of the SRAM device when a word line of the SRAM device is activated. The negative voltage generator includes an output terminal coupled to access transistors, a current path for discharging the output terminal up to a ground voltage level in response to control signals, and a pump for pumping the output terminal to make the output terminal be in a negative voltage level.

摘要翻译： 根据本发明的SRAM器件执行稳定的数据锁存操作。 本发明提供一种负电压发生器，其耦合到SRAM器件中的驱动晶体管，用于在SRAM器件的字线被激活时在SRAM器件的读周期期间为驱动晶体管提供负电压。 负电压发生器包括耦合到存取晶体管的输出端子，用于响应于控制信号将输出端子放电到地电压电平的电流路径，以及用于泵浦输出端子以使输出端子为负的电流 电压电平。

公开(公告)号：US5712821A

公开(公告)日：1998-01-27

申请号：US673524

申请日：1996-07-01

申请人： Douk Hyoun Ryu ,  Taek Moo Kim

发明人： Douk Hyoun Ryu ,  Taek Moo Kim

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C29/84

摘要： A redundancy circuit of a semiconductor memory device is provided, including: a plurality of repairing word lines for repairing the normal word line connected to a failed cell; a plurality of repairing paths for selecting a random repairing word line of the repairing word lines; and at least one comparing means for enabling at least two repairing word lines in case the respective paths corresponding to the same address on the normal decoding path and the repairing path are simultaneously enabled, whereby the normal word line of the failed cell is simultaneously enabled with at least two repairing word lines.

摘要翻译： 提供了一种半导体存储器件的冗余电路，包括：多个修复字线，用于修复连接到故障单元的正常字线; 用于选择修复字线的随机修复字线的多个修复路径; 以及至少一个比较装置，用于在与正常解码路径和修复路径上的相同地址对应的各个路径同时使能的情况下使能至少两个修复字线，从而同时使能故障小区的正常字线 至少两个维修字线。

公开(公告)号：US06272059B1

公开(公告)日：2001-08-07

申请号：US09468786

申请日：1999-12-21

申请人： Douk Hyoun Ryu ,  Yong Ho Seol

发明人： Douk Hyoun Ryu ,  Yong Ho Seol

IPC分类号： G11C700

CPC分类号： G11C7/065 ,  G11C7/12

摘要： A bit line sense-amplifier for a semiconductor memory device and a method for driving the same do not apply a bit line precharge voltage by a switch in an equalization operation, perform an equalization operation by interconnecting a plurality of sense-amplifier lines, then perform a precharge operation by applying a bit line precharge voltage through NMOS transistor of the switch, increase a sensing speed by reducing a loading of a sense-amplifier, reduce a transient current, and minimize a power-consumption by performing a precharge operation after a bit line equalization.

摘要翻译： 用于半导体存储器件的位线读出放大器及其驱动方法在均衡操作中不通过开关施加位线预充电电压，通过互连多个读出放大器线执行均衡操作，然后执行 通过施加开关的NMOS晶体管的位线预充电电压进行预充电操作，通过减小感测放大器的负载来降低感测速度，减少瞬态电流，并且通过在一位之后执行预充电操作来最小化功耗 线均衡。