公开(公告)号：US20100202220A1

公开(公告)日：2010-08-12

申请号：US12692512

申请日：2010-01-22

申请人： Kuoyuan Peter HSU ,  TaeHyung Jung ,  Douk Hyoun Ryu ,  Young Suk Kim

发明人： Kuoyuan Peter HSU ,  TaeHyung Jung ,  Douk Hyoun Ryu ,  Young Suk Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/4076

摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.

摘要翻译： 存储电路包括至少一个用于存储表示数据的电荷的存储单元。 存储单元与字线和第一位线耦合。 至少一个位线均衡晶体管耦合在第一位线和第二位线之间。 位线均衡电路与位线均衡晶体管耦合。 位线均衡电路被配置为向位线均衡晶体管提供脉冲，以在存储单元的访问周期之前的待机期间基本上均衡第一位线和第二位线的电压。

公开(公告)号：US08279686B2

公开(公告)日：2012-10-02

申请号：US12692512

申请日：2010-01-22

申请人： Kuoyuan Peter Hsu ,  TaeHyung Jung ,  Douk Hyoun Ryu ,  Young Suk Kim

发明人： Kuoyuan Peter Hsu ,  TaeHyung Jung ,  Douk Hyoun Ryu ,  Young Suk Kim

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/4076

摘要： A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.

摘要翻译： 存储电路包括至少一个用于存储表示数据的电荷的存储单元。 存储单元与字线和第一位线耦合。 至少一个位线均衡晶体管耦合在第一位线和第二位线之间。 位线均衡电路与位线均衡晶体管耦合。 位线均衡电路被配置为向位线均衡晶体管提供脉冲，以在存储单元的访问周期之前的待机期间基本上均衡第一位线和第二位线的电压。

公开(公告)号：US08902676B2

公开(公告)日：2014-12-02

申请号：US13457065

申请日：2012-04-26

申请人： TaeHyung Jung ,  BokMoon Kang

发明人： TaeHyung Jung ,  BokMoon Kang

IPC分类号： G11C7/10 ,  G11C5/06 ,  G11C16/24 ,  G11C7/12 ,  G11C16/26 ,  G11C8/08

CPC分类号： G11C8/08 ,  G11C5/063 ,  G11C7/12 ,  G11C16/24 ,  G11C16/26

摘要： A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential.

摘要翻译： 半导体存储器包括具有耦合到字线和位线的存储器单元的存储器阵列。 每个字线都有一个左端和一个相反的右端。 每两个相邻字线中的第一个字线的左端连接到左行驱动器，其右端连接到右钳位电路，每两​​个相邻字线中的第二个字线的右端连接到右排驱动器， 左端连接到左钳位电路，使得当右钳位电路被激活时，右钳位电路将相应的字线端钳位到预定电位，并且当左钳位电路被激活时，左钳位电路钳位相应的字线 结束到预定的电位。

公开(公告)号：US20130286754A1

公开(公告)日：2013-10-31

申请号：US13457065

申请日：2012-04-26

申请人： TaeHyung Jung ,  BokMoon Kang

发明人： TaeHyung Jung ,  BokMoon Kang

IPC分类号： G11C8/08

CPC分类号： G11C8/08 ,  G11C5/063 ,  G11C7/12 ,  G11C16/24 ,  G11C16/26

摘要： A semiconductor memory includes a memory array having memory cells coupled to wordlines and bitlines. Each wordline has a left end and an opposing right end. A first wordline in every two adjacent wordlines has its left end connected to a left row driver and its right end connected to a right clamp circuit, and a second wordline in every two adjacent wordlines has its right end connected to a right row driver and its left end connected to a left clamp circuit, such that when the right clamp circuits are activated, the right clamp circuits clamp the corresponding wordline ends to a predetermined potential, and when the left clamp circuits are activated, the left clamp circuits clamp the corresponding wordline ends to the predetermined potential.

摘要翻译： 半导体存储器包括具有耦合到字线和位线的存储器单元的存储器阵列。 每个字线都有一个左端和一个相反的右端。 每两个相邻字线中的第一个字线的左端连接到左行驱动器，其右端连接到右钳位电路，每两​​个相邻字线中的第二个字线的右端连接到右排驱动器， 左端连接到左钳位电路，使得当右钳位电路被激活时，右钳位电路将相应的字线端钳位到预定电位，并且当左钳位电路被激活时，左钳位电路钳位相应的字线 结束到预定的电位。

公开(公告)号：US20140003175A1

公开(公告)日：2014-01-02

申请号：US13540227

申请日：2012-07-02

申请人： TaeHyung Jung ,  KeeSoo Kim

发明人： TaeHyung Jung ,  KeeSoo Kim

IPC分类号： G11C7/02 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C7/08 ,  G11C29/025

摘要： A semiconductor memory includes a circuit block that is configured to receive a test mode command, a first sense amplifier that is coupled to sense and amplify a state of a first memory cell when enabled, and a second sense amplifier that is coupled to sense and amplify a state of a second memory cell when enabled. In an active cycle, the circuit block generates one or more control signals in response to the test mode command that cause the second sense amplifier to be enabled a predetermined amount of time after the first sense amplifier is enabled.

摘要翻译： 半导体存储器包括被配置为接收测试模式命令的电路块，耦合以在使能时耦合以感测和放大第一存储器单元的状态的第一读出放大器，以及耦合到感测和放大的第二读出放大器 启用时第二存储器单元的状态。 在有效周期中，电路块根据测试模式命令产生一个或多个控制信号，该命令使第二读出放大器在第一读出放大器被使能之后能够被预定的时间使能。

公开(公告)号：US08861294B2

公开(公告)日：2014-10-14

申请号：US13540227

申请日：2012-07-02

申请人： TaeHyung Jung ,  KeeSoo Kim

发明人： TaeHyung Jung ,  KeeSoo Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/02 ,  G11C7/08 ,  G11C29/025

摘要： A semiconductor memory includes a circuit block that is configured to receive a test mode command, a first sense amplifier that is coupled to sense and amplify a state of a first memory cell when enabled, and a second sense amplifier that is coupled to sense and amplify a state of a second memory cell when enabled. In an active cycle, the circuit block generates one or more control signals in response to the test mode command that cause the second sense amplifier to be enabled a predetermined amount of time after the first sense amplifier is enabled.

摘要翻译： 半导体存储器包括被配置为接收测试模式命令的电路块，耦合以在使能时耦合以感测和放大第一存储器单元的状态的第一读出放大器，以及耦合到感测和放大的第二读出放大器 启用时第二存储器单元的状态。 在有效周期中，电路块根据测试模式命令产生一个或多个控制信号，该命令使第二读出放大器在第一读出放大器被使能之后能够被预定的时间使能。

公开(公告)号：US07592858B1

公开(公告)日：2009-09-22

申请号：US12103332

申请日：2008-04-15

申请人： TaeHyung Jung

发明人： TaeHyung Jung

IPC分类号： G05F1/10

CPC分类号： H03K5/08 ,  H03K17/08122 ,  H03K19/00315

摘要： Circuit and method for a gate control output circuit having reduced voltage stress on the devices is disclosed. In a circuit of MOS transistors for supplying an output to control a transfer gate, the output having a high voltage level that exceeds a supply voltage, first and second clamping circuits are provided. The first clamping circuit ensures a voltage between the gate and the source/drain and drain/source of a PMOS transistor that couples a pumped voltage to the output does not exceed a predetermined voltage. The second clamping circuit ensures that the voltage between the gate of an NMOS transistor and the output which is coupled to the drain/source of the NMOS transistor does not exceed a predetermined amount. The clamping circuits prevent gate stress problems on the transistors by ensuring the voltages between the gates and the source/drain and drain/source terminals do not exceed predetermined voltages.

摘要翻译： 公开了一种在器件上具有降低的电压应力的栅极控制输出电路的电路和方法。 在用于提供输出以控制传输门的MOS晶体管的电路中，提供具有超过电源电压的高电压电平的输出，第一和第二钳位电路。 第一钳位电路确保栅极与将泵浦电压耦合到输出的PMOS晶体管的源极/漏极和漏极/源极之间的电压不超过预定电压。 第二钳位电路确保NMOS晶体管的栅极和耦合到NMOS晶体管的漏极/源极的输出之间的电压不超过预定量。 钳位电路通过确保栅极和源极/漏极和漏极/源极端子之间的电压不超过预定电压来防止晶体管上的栅极应力问题。