公开(公告)号：US09023724B2

公开(公告)日：2015-05-05

申请号：US13601785

申请日：2012-08-31

Applicant: Duk Eui Lee ,  Seung Cheol Lee

Inventor： Duk Eui Lee ,  Seung Cheol Lee

IPC: H01L27/115 ,  H01L21/768 ,  H01L21/02 ,  C11D11/00

CPC classification number: H01L27/11521 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/76814 ,  H01L21/7682

Abstract: A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer.

Abstract translation: 一种制造半导体存储器件的方法包括在半导体衬底上形成多个栅极线，在栅极线上形成绝缘层，并使用粘度低于2cP的无表面活性剂的清洁溶液进行清洁处理，以及 酸性低于3的pH值以除去绝缘层表面的残留物。

公开(公告)号：US20130164926A1

公开(公告)日：2013-06-27

申请号：US13601676

申请日：2012-08-31

Applicant: Duk Eui LEE

Inventor： Duk Eui LEE

IPC: H01L21/336

CPC classification number: H01L27/11524 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming first and second gate lines over a semiconductor substrate, wherein each second gate line has a greater width than each of the first gate lines, forming a first insulating layer surrounding the top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines and between the first gate lines, forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer, removing the first reaction region, forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer, and removing the second reaction regions exposing a portion of each first and second gate lines.

Abstract translation: 一种制造半导体器件的方法包括在半导体衬底上形成第一和第二栅极线，其中每个第二栅极线具有比每个第一栅极线更大的宽度，形成围绕第一栅极线的顶壁和侧壁的第一绝缘层 以及第二栅极线，使得在第一和第二栅极线之间和第一栅极线之间形成第一气隙，通过使腐蚀剂扩散到小于目标深度的深度从而形成第一绝缘层中的第一反应区域 去除所述第一反应区域，通过从所述第一绝缘层的表面扩散所述蚀刻剂到所述目标深度，在所述第一绝缘层中形成第二反应区域，以及除去暴露所述第一绝缘层的每一个的一部分的所述第二反应区域 第一和第二栅极线。

公开(公告)号：US08865562B2

公开(公告)日：2014-10-21

申请号：US13601676

申请日：2012-08-31

Applicant: Duk Eui Lee

Inventor： Duk Eui Lee

IPC: H01L21/764 ,  H01L27/115

CPC classification number: H01L27/11524 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming first and second gate lines over a semiconductor substrate, wherein each second gate line has a greater width than each of the first gate lines, forming a first insulating layer surrounding the top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines and between the first gate lines, forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer, removing the first reaction region, forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer, and removing the second reaction regions exposing a portion of each first and second gate lines.

Abstract translation: 一种制造半导体器件的方法包括在半导体衬底上形成第一和第二栅极线，其中每个第二栅极线具有比每个第一栅极线更大的宽度，形成围绕第一栅极线的顶壁和侧壁的第一绝缘层 以及第二栅极线，使得在第一和第二栅极线之间和第一栅极线之间形成第一气隙，通过使腐蚀剂扩散到小于目标深度的深度从而形成第一绝缘层中的第一反应区域 去除所述第一反应区域，通过从所述第一绝缘层的表面扩散所述蚀刻剂到所述目标深度，在所述第一绝缘层中形成第二反应区域，以及除去暴露所述第一绝缘层的每一个的一部分的所述第二反应区域 第一和第二栅极线。

公开(公告)号：US20130164925A1

公开(公告)日：2013-06-27

申请号：US13601785

申请日：2012-08-31

Applicant: Duk Eui LEE ,  Seung Cheol LEE

Inventor： Duk Eui LEE ,  Seung Cheol LEE

IPC: H01L21/306

CPC classification number: H01L27/11521 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/76814 ,  H01L21/7682

Abstract: A method of manufacturing a semiconductor memory device comprises forming a plurality of gate lines on a semiconductor substrate, forming an insulating layer on the gate lines, and performing a cleaning process using a surfactant-free cleaning solution having a viscosity of lower than 2 cP and an acidity of lower than 3 pH to remove residue from the surface of the insulating layer.

Abstract translation: 一种制造半导体存储器件的方法包括在半导体衬底上形成多个栅极线，在栅极线上形成绝缘层，并使用粘度低于2cP的无表面活性剂的清洁溶液进行清洁处理，以及 酸性低于3的pH值以除去绝缘层表面的残留物。