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公开(公告)号：US20050160127A1
公开(公告)日：2005-07-21
申请号：US10979775
申请日：2004-11-02
CPC分类号： G06F17/142
摘要： A modular pipeline algorithm and architecture for computing discrete Fourier transforms is described. For an N point transform, two pipeline N point {square root}{square root over (N)} point fast Fourier transform modules are combined with a center element. The center element contains memories, multipliers and control logic. Compared with standard N point pipeline FFT, the modular pipeline FFT maintains the bandwidth existing pipeline FFTs with reduced dynamic power consumption and reduced complexity of the overall hardware pipeline.
摘要翻译： 描述了用于计算离散傅立叶变换的模块化流水线算法和架构。 对于N点变换，两个流水线N点{平方根} {平方根（N点快速傅立叶变换模块与中心元素组合），中心元素包含存储器，乘法器和控制逻辑，与标准N点流水线FFT ，模块化管线FFT维持带宽现有流水线FFT，具有降低的动态功耗和降低整体硬件流水线的复杂性。
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公开(公告)号：US08161090B2
公开(公告)日：2012-04-17
申请号：US12329023
申请日：2008-12-05
IPC分类号： G06F7/487
摘要： In a particular embodiment, a method is disclosed that includes receiving first and second operands at a floating-point fused add-subtract circuit. The method further includes simultaneously performing add and subtract operations on the first and second operands via the floating-point fused add-subtract circuit to produce a sum result output and a difference result output. The floating-point fused add-subtract circuit includes sign logic, exponent adjustment logic, and shift logic that are shared by an add/round and post-normalize circuit and a subtract/round and post-normalize circuit to produce the sum and difference result outputs.
摘要翻译： 在特定实施例中，公开了一种包括在浮点加法减法电路处接收第一和第二操作数的方法。 该方法还包括经由浮点加法减法电路同时对第一和第二操作数执行加法和减法运算，以产生和结果输出和差分结果输出。 浮点加法减法电路包括由加法/回归和归一化后电路共享的符号逻辑，指数调整逻辑和移位逻辑，以及减法/回合和后归一化电路以产生和差和差分结果 输出。
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3.发明申请公开(公告)号：US20070132490A1
公开(公告)日：2007-06-14
申请号：US11299974
申请日：2005-12-12
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03H11/483 , H03L7/093
摘要： A method and apparatus for capacitance multiplication using two charge pumps. A first charge pump (206) provides a current signal (1216) that is first conducted by a resistor (310) of an RC network and then split into three current paths prior to being conducted by a capacitor of the RC network. A first current path provides current to the capacitor (306) of the RC network from node (320). A second current path multiplies the current conducted by capacitor (306) by a first current multiplication factor. A third current path provides current to a second charge pump, which multiplies the current from the first charge pump by a second current multiplication factor that has a fractional value with an inverse magnitude sign relative to the first current multiplication factor. The combination of the second and third current paths effectively multiplies the capacitance magnitude of capacitor (306).
摘要翻译： 一种使用两个电荷泵进行电容倍增的方法和装置。 第一电荷泵（206）提供首先由RC网络的电阻器（310）传导的电流信号（1216），然后在被RC网络的电容器传导之前被分成三个电流路径。 第一电流路径从节点（320）向RC网络的电容器（306）提供电流。 第二电流路径将由电容器（306）传导的电流乘以第一电流倍增因子。 第三电流路径向第二电荷泵提供电流，该第二电荷泵将来自第一电荷泵的电流乘以具有相对于第一当前倍增因子具有相反幅度符号的分数值的第二电流倍增因子。 第二和第三电流路径的组合有效地乘以电容器的电容量（306）。
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公开(公告)号：US20070214204A1
公开(公告)日：2007-09-13
申请号：US11370783
申请日：2006-03-08
申请人： Earl Swartzlander
发明人： Earl Swartzlander
IPC分类号： G06F7/38
CPC分类号： G06F7/53 , G06F7/38 , G06F7/4991 , G06F7/5336 , G06F2207/3832
摘要： The present invention provides a solution to the shortcomings of the traditional two's complement system that is commonly utilized in modern computing systems and digital signal processors. The previously described shortcoming of the two's complement system are corrected in the present invention is a number system described as the negative two's complement system. In the negative two's complement system a n-bit number, A, has a sign bit, an-1, and n−1 fractional bits, an-2, an-3, . . . , a0. The value of an n-bit fractional negative two's complement number is: A = a n - 1 + ∑ i = 0 n - 2 - a i 2 i - n + 1 .
摘要翻译： 本发明提供了在现代计算系统和数字信号处理器中通常使用的传统二进制补码系统的缺点的解决方案。 在本发明中纠正了前面描述的二进制补码系统的缺点是被描述为负二进制补码系统的数字系统。 在负二进制补码系统中，n比特数字A具有符号位，第n-1个和第n-1个小数位，一个第n-2个子位， n-3，...， 。 。 ，<0> 。 n位分数负二进制补码的值为：
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公开(公告)号：US08166091B2
公开(公告)日：2012-04-24
申请号：US12268136
申请日：2008-11-10
申请人： Earl Swartzlander, Jr. , Hani Saleh
发明人： Earl Swartzlander, Jr. , Hani Saleh
CPC分类号： G06F7/483 , G06F7/5443 , G06F17/142 , G06F17/16
摘要： In an embodiment, a dot-product unit to perform single-precision floating-point product and addition operations is disclosed that includes a first multiplier tree unit adapted to multiply first and second significand operands to produce a first set of two partial products. The dot-product unit further includes a second multiplier tree unit adapted to multiply third and fourth significand operands to produce a second set of two partial products, a shared exponent compare unit adapted to compare exponents of the first, second, third and fourth operands to produce an alignment shift value, and an alignment unit adapted to shift the second set of two partial products based on the alignment shift value. The dot-product unit also includes an adder unit adapted to add or subtract the first set of two partial products and the second shifted set of two partial products to produce a dot-product value that is a single-precision floating-point value.
摘要翻译： 在一个实施例中，公开了一种用于执行单精度浮点乘积和加法运算的点积单元，其包括适于乘以第一和第二有效位操作数以产生第一组两个部分乘积的第一乘法器树单元。 点产品单元还包括第二乘法器树单元，其适于乘以第三和第四有效位操作数以产生第二组两个部分乘积，共享指数比较单元，适于将第一，第二，第三和第四操作数的指数与 产生对准偏移值，以及对准单元，其适于基于对准偏移值移动第二组两个部分积。 点产品单元还包括加法器单元，其适于加法或减去第一组两个部分乘积和第二移位的两个部分乘积的集合以产生作为单精度浮点值的点积值。
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