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    METHOD OF PERFORMING A NUMERICAL SOLVING PROCESS
    1.
    发明公开
    METHOD OF PERFORMING A NUMERICAL SOLVING PROCESS 审中-公开

    公开(公告)号：US20240319961A1

    公开(公告)日：2024-09-26

    申请号：US18573361

    申请日：2022-07-01

    Applicant: Talos Innovation ApS

    Inventor： Finlay Bertram

    IPC: G06F7/38 ,  G01V20/00 ,  G06F30/27

    CPC classification number: G06F7/38 ,  G01V20/00 ,  G06F30/27

    Abstract: A computer-implemented method of performing an a numerical solving process using a numerical solver for one or more times steps to obtain a numerical solution for each of the one or more time steps, wherein performing the numerical solving process at each time step comprises providing an initial estimate to the numerical solver and applying the numerical solver to a set of equations representative of a real or virtual process or system, wherein the method comprises, for a current time step of the one or more time steps: obtaining time step information for the current time step: predicting an initial estimate for a subsequent time step using the obtained current time step information wherein predicting the initial estimate uses a predictive model characterised by one or more model parameters that are pre-determined using a statistical and/or machine learning derived process; and performing a numerical solving process using the numerical solver for the subsequent time step thereby to obtain a numerical solution for the subsequent time step, wherein performing the numerical solving process comprises providing at least the predicted initial estimate to the numerical solver.

    Processing with compact arithmetic processing element
    2.
    发明授权
    Processing with compact arithmetic processing element 有权

    公开(公告)号：US11768660B2

    公开(公告)日：2023-09-26

    申请号：US18102020

    申请日：2023-01-26

    Applicant: Singular Computing LLC

    Inventor： Joseph Bates

    IPC: G06F7/483 ,  G06F7/523 ,  H03K19/17728 ,  G06F7/38

    CPC classification number: G06F7/483 ,  G06F7/38 ,  G06F7/4833 ,  G06F7/5235 ,  H03K19/17728

    Abstract: A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).

    PROCESSING WITH COMPACT ARITHMETIC PROCESSING ELEMENT
    3.
    发明公开
    PROCESSING WITH COMPACT ARITHMETIC PROCESSING ELEMENT 审中-公开

    公开(公告)号：US20230168861A1

    公开(公告)日：2023-06-01

    申请号：US18102020

    申请日：2023-01-26

    Applicant: Singular Computing LLC

    Inventor： Joseph Bates

    IPC: G06F7/483 ,  G06F7/523 ,  G06F7/38 ,  H03K19/17728

    CPC classification number: G06F7/483 ,  G06F7/4833 ,  G06F7/5235 ,  G06F7/38 ,  H03K19/17728

    Abstract: A processor or other device, such as a programmable and/or massively parallel processor or other device, includes processing elements designed to perform arithmetic operations (possibly but not necessarily including, for example, one or more of addition, multiplication, subtraction, and division) on numerical values of low precision but high dynamic range (“LPHDR arithmetic”). Such a processor or other device may, for example, be implemented on a single chip. Whether or not implemented on a single chip, the number of LPHDR arithmetic elements in the processor or other device in certain embodiments of the present invention significantly exceeds (e.g., by at least 20 more than three times) the number of arithmetic elements, if any, in the processor or other device which are designed to perform high dynamic range arithmetic of traditional precision (such as 32 bit or 64 bit floating point arithmetic).

    DISTRIBUTED DOUBLE-PRECISION FLOATING-POINT ADDITION
    4.
    发明申请
    DISTRIBUTED DOUBLE-PRECISION FLOATING-POINT ADDITION 审中-公开

    公开(公告)号：US20180329706A1

    公开(公告)日：2018-11-15

    申请号：US16042910

    申请日：2018-07-23

    Applicant: Intel Corporation

    Inventor： Martin Langhammer

    IPC: G06F9/30

    CPC classification number: G06F9/30014 ,  G06F7/38 ,  G06F7/485

    Abstract: The present embodiments relate to circuitry that efficiently performs double-precision floating-point addition operations, single-precision floating-point addition operations, and fixed-point addition operations. Such circuitry may be implemented in specialized processing blocks. If desired, each specialized processing block may efficiently perform a single-precision floating-point addition operation, and multiple specialized processing blocks may be coupled together to perform a double-precision floating-point addition operation. In some embodiments, four specialized processing blocks that are arranged in a one-way cascade chain may compute the sum of two double-precision floating-point number. If desired, two specialized processing blocks that are arranged in a two-way cascade chain may compute the sum of two double-precision floating-point numbers.

    MAJORITY CIRCUIT
    6.
    发明申请
    MAJORITY CIRCUIT 审中-公开

    公开(公告)号：US20180246849A1

    公开(公告)日：2018-08-30

    申请号：US15758097

    申请日：2015-11-25

    Applicant: HITACHI, LTD.

    Inventor： Takuya OKUYAMA ,  Masanao YAMAOKA

    IPC: G06F17/10 ,  H03K19/23 ,  G06F7/38

    CPC classification number: G06F17/10 ,  G06F7/38 ,  H03K19/23

    Abstract: An object of the invention is to provide a majority circuit which may be manufactured cheaply and easily and may process necessary majority functions for calculation in an interaction model. The majority circuit according to the invention simplifies the processing of the majority function by using a bitonic sort circuit to round the sum of input signals to a power of 2.

    RATE DOMAIN NUMERICAL PROCESSING CIRCUIT AND METHOD
    9.
    发明申请
    RATE DOMAIN NUMERICAL PROCESSING CIRCUIT AND METHOD 审中-公开

    公开(公告)号：US20170344341A1

    公开(公告)日：2017-11-30

    申请号：US15167346

    申请日：2016-05-27

    Applicant: Raytheon Company

    Inventor： Harry Bourne Marr, JR. ,  Jeffery Jay Logan ,  Daniel Thompson

    IPC: G06F7/38

    CPC classification number: G06F7/38 ,  G06F7/68 ,  G06F2207/481

    Abstract: Rate domain numerical processing comprises receiving an input serial data stream on a single input wire in which a multi-valued number is represented as a rate of pulse events comprising pulses, null pulses or a combination thereof. The rate of pulse events in an output serial data stream is varied in accordance with an operand to perform a multi-valued arithmetic operation selected from multiplication, division, addition and subtraction or a combination thereof. The rate may be varied by scaling the rate by an operand, which may be implemented using a count and compare circuit topology. The output serial data stream is output on a single output wire. The rate domain operations, specifically multiplication and division are accomplished without the resource & power intensive binary multiplier and binary divisions circuits. The operations are implemented using simple registers, adders, accumulators, counters, comparators, and basic logic, which is far more SWaP-C efficient.

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