公开(公告)号：US4815039A

公开(公告)日：1989-03-21

申请号：US142388

申请日：1988-01-11

Applicant: Jy-Der Tai ,  Edison Chiu

Inventor： Jy-Der Tai ,  Edison Chiu

IPC: G06F5/06 ,  G06F5/10 ,  G06F5/14 ,  G06F12/00 ,  G11C7/00 ,  G11C13/00

CPC classification number: G06F5/14

Abstract: An arbiter (52) is operable to supply an up/down signal (11) and a clock signal (13) to an up/down counter (10) so that the up/down counter (10) can count the difference between read requests (54) and write requests (56) experienced by an associated FIFO memory.The arbiter (52) is operable to receive asynchronous read and write requests (54, 56) that are closely spaced in time or appear simultaneously, and to store the read request in a read latch (104) and the write request in a write latch (92). A decision circuit (62) is operable to determine priority between the read and write requests, and processes the request that is awarded priority. Once the first priority request has been processed, the stored second non-priority request is then processed.

Abstract translation: 仲裁器（52）可操作以向上/向下计数器（10）提供上/下信号（11）和时钟信号（13），使得上/下计数器（10）可以计数读请求之间的差 （54）和由相关FIFO存储器经历的写入请求（56）。 仲裁器（52）可操作以接收在时间上紧密间隔或同时出现的异步读和写请求（54,56），并将读请求存储在读锁存器（104）中，并且写请求在写锁存器 （92）。 判定电路（62）可操作以确定读取和写入请求之间的优先级，并处理被授予优先权的请求。 一旦处理了第一优先请求，则处理存储的第二非优先级请求。

公开(公告)号：US5021994A

公开(公告)日：1991-06-04

申请号：US142374

申请日：1988-01-11

Applicant: Jy-Der Tai ,  Edison Chiu ,  Quang-Dieu An ,  Te-Chuan Hsu

Inventor： Jy-Der Tai ,  Edison Chiu ,  Quang-Dieu An ,  Te-Chuan Hsu

IPC: G06F5/10 ,  G06F5/14 ,  G06F7/62 ,  H03K21/12 ,  H03K21/38

CPC classification number: G06F5/14 ,  G06F7/62 ,  H03K21/12 ,  H03K21/38

Abstract: A look-ahead flag generator generates a flag signal corresponding to the occurrence of a predetermined value stored in a counter (10). The output of the counter outputs any of a plurality of values, the values including the predetermined value and at least one boundary value that is one unit of increment or decrement displaced from the predetermined value. A clock signal source (13) is coupled to a first input of the counter (10) to indicate a decrement or an increment to the value stored in the counter (10). An up/down signal source (11) is coupled to a second input of the counter to indicate whether an increment or a decrement of the stored value should be performed. Predetermined states of the up/down signal and the clock signal are operable to cause a boundary value stored in the counter (10) to be changed to the predetermined value. A predecoder (12) is coupled to an output of counter (10) for decoding the boundary value. A latch (132) stores the decoded boundary value. A gate circuit (111, 117, 139) is coupled to the latch (132), a flag signal output, the up/down signal source (11) and the clock signal source (13) and is operable to generate the flag signal in response to the stored decoded boundary value and the predetermined states of the up/down signal and the clock signal.

Abstract translation: 先行标志生成器生成与存储在计数器（10）中的预定值的出现相对应的标志信号。 计数器的输出输出多个值中的任何值，包括预定值的值和作为从预定值偏移的增量或减量的一个单位的至少一个边界值。 时钟信号源（13）耦合到计数器（10）的第一输入，以指示对存储在计数器（10）中的值的递减或增量。 上/下信号源（11）耦合到计数器的第二输入端，以指示是否应执行存储值的增量或减量。 上/下信号和时钟信号的预定状态可操作以使存储在计数器（10）中的边界值变为预定值。 预解码器（12）耦合到计数器（10）的输出端，用于解码边界值。 锁存器（132）存储解码的边界值。 门电路（111,117,139）耦合到锁存器（132），标志信号输出，上/下信号源（11）和时钟信号源（13），并可操作以产生标志信号 响应于存储的解码边界值和上/下信号和时钟信号的预定状态。

公开(公告)号：US4933901A

公开(公告)日：1990-06-12

申请号：US280113

申请日：1988-12-05

Applicant: Jy-Der Tai ,  Edison Chiu

Inventor： Jy-Der Tai ,  Edison Chiu

IPC: G06F5/10 ,  G06F5/14

CPC classification number: G06F5/14

Abstract: An arbiter (52) is operable to supply an up/down signal (11) and a clock signal (13) to an up/down counter (10) so that the up/down counter (10) can count the difference between read requests (54) and write requests (56) experienced by an associated FIFO memory.The arbiter (52) is operable to receive asynchronous read and write requests (54, 56) that are closely spaced in time or appear simultaneously, and to store the read request in a read latch (104) and the write request in a write latch (92). A decision circuit (62) is operable to determine priority between the read and write requests, and processes the request that is awarded priority. Once the first priority request has been processed, the stored non-priority request is then processed.

Abstract translation: 仲裁器（52）可操作以向上/向下计数器（10）提供上/下信号（11）和时钟信号（13），使得上/下计数器（10）可以计数读请求之间的差 （54）和由相关FIFO存储器经历的写入请求（56）。 仲裁器（52）可操作以接收在时间上紧密间隔或同时出现的异步读和写请求（54,56），并将读请求存储在读锁存器（104）中，并且写请求在写锁存器 （92）。 判定电路（62）可操作以确定读取和写入请求之间的优先级，并处理被授予优先权的请求。 一旦处理了第一优先请求，则处理所存储的非优先级请求。