公开(公告)号：US20060033155A1

公开(公告)日：2006-02-16

申请号：US10916133

申请日：2004-08-11

申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。

公开(公告)号：US07122876B2

公开(公告)日：2006-10-17

申请号：US10916133

申请日：2004-08-11

申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

IPC分类号： H01L29/00

CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。

公开(公告)号：US20060220179A1

公开(公告)日：2006-10-05

申请号：US11097744

申请日：2005-04-01

申请人： You-Kuo Wu ,  Edward Chiang

发明人： You-Kuo Wu ,  Edward Chiang

IPC分类号： H01L29/00

CPC分类号： H01L29/0882 ,  H01L29/0878 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A method for forming an improved isolation junction in an LDMOS structure to reduce current leakage at high operating Voltages including forming doped regions in a buried layer prior to forming an overlying epitaxial region including doped isolation regions followed by a drive-in process to form a continuous isolation region by intermixing the doped regions formed in the buried layer with the overlying doped isolation regions.

摘要翻译： 一种用于在LDMOS结构中形成改进的隔离结的方法，以减少在高工作电压下的电流泄漏，包括在形成包含掺杂隔离区域的上覆外延区域之前形成掩埋层中的掺杂区域，随后进行形成连续 通过将形成在掩埋层中的掺杂区域与上覆的掺杂隔离区域相混合来实现。

公开(公告)号：US20060286735A1

公开(公告)日：2006-12-21

申请号：US11505957

申请日：2006-08-17

申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

IPC分类号： H01L21/8234

CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。

公开(公告)号：US07384836B2

公开(公告)日：2008-06-10

申请号：US11505957

申请日：2006-08-17

申请人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

发明人： You-Kuo Wu ,  Edward Chiang ,  Shun-Liang Hsu

IPC分类号： H01L21/8234

CPC分类号： H01L29/0852 ,  H01L21/74 ,  H01L21/7621 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A transistor of an integrated circuit is provided. A first doped well region is formed in a well layer at a first active region. At least part of the first doped well region is adjacent to a gate electrode of the transistor. A recess is formed in the first doped well region, and the recess preferably has a depth of at least about 500 angstroms. A first isolation portion is formed on an upper surface of the well layer at least partially over an isolation region. A second isolation portion is formed at least partially in the recess of the first doped well region. At least part of the second isolation portion is lower than the first isolation portion. A drain doped region is formed in the recess of the first doped well region. The second isolation portion is located between the gate electrode and the drain doped region.

摘要翻译： 提供集成电路的晶体管。 在第一有源区的阱层中形成第一掺杂阱区。 第一掺杂阱区的至少一部分与晶体管的栅电极相邻。 在第一掺杂阱区中形成凹槽，并且凹槽优选地具有至少约500埃的深度。 第一隔离部分至少部分地在隔离区域上形成在阱层的上表面上。 至少部分地在第一掺杂阱区的凹部中形成第二隔离部分。 第二隔离部分的至少一部分比第一隔离部分低。 漏极掺杂区形成在第一掺杂阱区的凹槽中。 第二隔离部分位于栅电极和漏极掺杂区之间。