Memory access system
    1.
    发明授权
    Memory access system 失效
    内存访问系统

    公开(公告)号:US4124891A

    公开(公告)日:1978-11-07

    申请号:US742814

    申请日:1976-11-18

    CPC分类号: G06F13/124

    摘要: An input/output processing system includes an input/output processing unit and a read only memory (ROM) and a read/write memory. The ROM is coded to include instructions of a number of control routines. The read/write memory includes locations for storing instructions and data. The processing unit includes a plurality of registers for storing information used in developing addresses for accessing each memory. It further includes a control register for storing information for controlling accesses to the memories and a steering register which operatively couples to the control register and stores information designating which one of the memories is to be accessed. The processing unit is conditioned to exclusively OR the information in the control register with the information contained in one of the plurality of registers. By logically combining the contents of the control register and contents of another register during each address development operation, the processing unit is able to switch between the two memories as desired. When it is desired to start or stop accessing instructions from ROM, the processing unit is conditioned to perform an OR or AND operation respectively upon the contents of the control register with the contents of the other register and place the result in the control register.

    摘要翻译: 输入/输出处理系统包括输入/​​输出处理单元和只读存储器(ROM)和读/写存储器。 ROM被编码为包括许多控制例程的指令。 读/写存储器包括用于存储指令和数据的位置。 处理单元包括多个用于存储用于开发用于访问每个存储器的地址的信息的寄存器。 它还包括用于存储用于控制对存储器的访问的信息的控制寄存器和可操作地耦合到控制寄存器并存储指定要访问哪个存储器的信息的指导寄存器。 处理单元被调节为将控制寄存器中的信息与包含在多个寄存器之一中的信息进行排他性或异或。 通过在每个地址开发操作期间逻辑地组合控制寄存器的内容和另一寄存器的内容,处理单元能够根据需要在两个存储器之间切换。 当希望从ROM开始或停止访问指令时,处理单元被调节为分别对具有另一个寄存器的内容的控制寄存器的内容执行“或”或“与”运算,并将结果存储在控制寄存器中。

    Input/output processing system utilizing locked processors
    2.
    发明授权
    Input/output processing system utilizing locked processors 失效
    使用锁定处理器的输入/输出处理系统

    公开(公告)号:US4099234A

    公开(公告)日:1978-07-04

    申请号:US741632

    申请日:1976-11-15

    摘要: An input/output system includes at least a pair of processing units and system interface apparatus for comparing the results produced by both halves of the pair during normal system operation under control of a main or host processing unit. The system interface apparatus includes comparison circuits for detecting a mis-compare between the results of each half and sequence control logic circuits which are conditioned upon the occurrence of a mis-compare to unlock or deconfigure the pair to establish in a predetermined manner which of the processing units is faulty. The system interface apparatus, following signal indications of a certain minimum confidence within a processing unit, continues testing of the processor using stored diagnostic routines to determine which one of the processing units is good. It then stops the operation of the bad processing unit and enables system operation to be continued with the good processing unit. To ensure reliable processing, both halves of the pair are tested when a miscompare cannot be related to an error condition associated with one of the pair notwithstanding the fact that the first processing unit tests well. Following reconfiguration, the operating system associated with the system provides periodic testing of the good processing unit, thereby ensuring that the system continues to operate reliably.

    摘要翻译: 输入/输出系统至少包括一对处理单元和系统接口装置,用于在主处理单元或主处理单元的控制下在正常系统操作期间比较两对的两半所产生的结果。 系统接口装置包括比较电路,用于检测每一半的结果与序列控制逻辑电路之间的错误比较,序列控制逻辑电路在发生误比较时进行解锁或解除配置,以预定的方式建立 处理单元有故障。 系统接口设备在处理单元内具有一定的最小置信度的信号指示,继续使用存储的诊断例程对处理器进行测试,以确定处理单元中的哪一个是良好的。 然后停止坏处理单元的操作,并使良好处理单元能够继续系统运行。 为了确保可靠的处理,尽管第一个处理单元测试良好,但是当误差比较不能与与该对中的一个相关联的错误状况不相关时,该对的两个部分被测试。 在重新配置之后,与系统相关联的操作系统提供良好处理单元的周期性测试,从而确保系统继续可靠地运行。