公开(公告)号：US4670859A

公开(公告)日：1987-06-02

申请号：US704412

申请日：1985-02-22

申请人： Makoto Furihata ,  Setsuo Ogura ,  Shizuo Kondo ,  Eiji Minamimura

发明人： Makoto Furihata ,  Setsuo Ogura ,  Shizuo Kondo ,  Eiji Minamimura

IPC分类号： G11C17/00 ,  H03K19/00 ,  H03K19/091

CPC分类号： H03K19/091 ,  H03K19/001

摘要： A logic circuit of a large scale which consumes small amounts of electric power is comprised of a plurality of ROM portions each formed of IIL circuits. Input signal lines are commonly used to transmit input signals to the ROM portions. The plurality of ROM portions are selectively operated by ROM select signals, and outputs corresponding to the input signals are obtained from a selected ROM portion. To select a particular ROM portion out of the plurality of ROM portions, the emitters of inverse npn transistors of IIL circuits constituting the selected ROM portion are rendered to assume ground potential. In the meantime, the emitters of the inverse npn transistors of IIL circuits in the non-selected ROM portions are held in a floating condition. This makes it possible to obtain a logic circuit which consumes small amounts of electric power with a very simple construction since the non-selected ROM portions consume no power.

摘要翻译： 消耗少量电力的大规模的逻辑电路包括由IIL电路形成的多个ROM部分。 输入信号线通常用于将输入信号发送到ROM部分。 多个ROM部分由ROM选择信号选择性地操作，并且从所选择的ROM部分获得对应于输入信号的输出。 为了选择多个ROM部分中的特定ROM部分，构成所选择的ROM部分的IIL电路的逆npn晶体管的发射极被呈现为地电位。 同时，未选择的ROM部分中的IIL电路的逆npn晶体管的发射极保持在浮置状态。 这使得可以以非常简单的结构获得消耗少量电力的逻辑电路，因为未选择的ROM部分不消耗电力。

公开(公告)号：US4725745A

公开(公告)日：1988-02-16

申请号：US643260

申请日：1984-08-22

申请人： Shizuo Kondo ,  Setsuo Ogura ,  Eiji Minamimura ,  Makoto Furihata

发明人： Shizuo Kondo ,  Setsuo Ogura ,  Eiji Minamimura ,  Makoto Furihata

IPC分类号： H01L27/112 ,  H03K19/0944 ,  H03K19/177 ,  H03K19/02 ,  G06F7/38 ,  H03K19/091

CPC分类号： H03K19/09448 ,  H01L27/112 ,  H03K19/17708

摘要： An integrated programmable logic array formed within a single silicon chip comprises a combination of a logical product gate array and a logical summation gate array. The logical product gate array is equipped with a plurality of MIS field-effect transistors whose gates are selectively driven by a plurality of input signals. Source-drain paths of these transistors are connected in series. The logical summation gate array is equipped with a plurality of inverted bipolar transistors having collector-emitter paths which are connected in parallel.

摘要翻译： 形成在单个硅芯片内的集成可编程逻辑阵列包括逻辑乘积门阵列和逻辑求和门阵列的组合。 逻辑积门阵列配备有多个MIS场效应晶体管，其栅极由多个输入信号选择性地驱动。 这些晶体管的源极 - 漏极路径串联连接。 逻辑求和门阵列配备有多个并联连接的集电极 - 发射极路径的反向双极晶体管。

公开(公告)号：US4659947A

公开(公告)日：1987-04-21

申请号：US665385

申请日：1984-10-26

申请人： Setsuo Ogura ,  Shizuo Kondo ,  Eiji Minamimura ,  Makoto Furihata

发明人： Setsuo Ogura ,  Shizuo Kondo ,  Eiji Minamimura ,  Makoto Furihata

IPC分类号： H03K19/091 ,  H03K19/177 ,  H03K19/082

CPC分类号： H03K19/17708

摘要： An integrated programmable logic array formed within a single silicon chip comprises a combination of an NAND or AND gate array and an NOR or OR gate array.The NAND or AND gate array includes a plurality of bipolar transistors which are driven to operate in the forward direction by a plurality of input signals, and a plurality of Schottky barrier diodes provided between the collectors of the bipolar transistors and output signal lines. The NOR or OR gate array includes a plurality of other bipolar transistors which are driven to operate in the backward direction by a plurality of output signals from the NAND or AND gate array.

摘要翻译： 形成在单个硅芯片内的集成可编程逻辑阵列包括NAND或与门阵列和NOR或OR门阵列的组合。 NAND或与门阵列包括多个双极晶体管，其被驱动以通过多个输入信号在正向工作，以及设置在双极晶体管的集电极和输出信号线之间的多个肖特基势垒二极管。 NOR或OR门阵列包括多个其它双极晶体管，其被驱动以通过来自NAND或与门阵列的多个输出信号在向后方向上工作。