公开(公告)号：US20060129739A1

公开(公告)日：2006-06-15

申请号：US11010205

申请日：2004-12-11

申请人： Eric Lais ,  Donald DeSota ,  Michael Grassi ,  Bruce Gilbert

发明人： Eric Lais ,  Donald DeSota ,  Michael Grassi ,  Bruce Gilbert

IPC分类号： G06F12/06

CPC分类号： G06F12/0653 ,  G06F13/1668

摘要： A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules within the ports; each port is capable of having a different number of memory modules relative to the other ports. The tables impose no restrictions on where the memory modules are to be inserted within the ports, both number-wise and position-wise. The tables are independently configurable; the configuration of each table is modifiable independently of the configurations of the other tables. Each table is dynamically configurable. The entries of a table are modifiable to reflect changes in the number and type of the memory modules connected, without restarting or temporarily halting the computer system containing the memory controller.

摘要翻译： 存储器控制器包括端口和对应的表。 每个端口都接受一个或多个内存模块。 每个表包括将内存地址映射到内存模块的条目。 每个条目对应于不超过一个内存模块。 这些表支持端口内存模块的非对称数量; 每个端口能够相对于其他端口具有不同数量的存储器模块。 这些表对数字和位置方面的内存模块在端口中插入的位置没有任何限制。 表可独立配置; 每个表的配置可以独立于其他表的配置进行修改。 每个表都是可动态配置的。 表的条目是可修改的，以反映连接的内存模块的数量和类型的变化，而不会重新启动或暂时中止包含内存控制器的计算机系统。

公开(公告)号：US07440523B2

公开(公告)日：2008-10-21

申请号：US11409636

申请日：2006-04-24

申请人： Eric Lais ,  Mark Greenberg ,  Manish Shah

发明人： Eric Lais ,  Mark Greenberg ,  Manish Shah

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H04L1/0052 ,  H04L1/0054 ,  H04L1/0069

摘要： An apparatus and method are described for mapping a plurality of multimedia streams (e.g., received from a set of satellite transponders) across a lesser plurality of decoders. In one embodiment, arbitration logic allocates the multimedia streams to divide the decoding load equally among the group of decoders (or at least as equally as possible). Allocation may occur statically, when the system is initialized, or dynamically, as the streams are being processed. In addition, in one embodiment, the arbitration logic monitors the amount of multimedia data for each stream stored in a buffer and causes streams to be serviced by the decoders which have relatively more stored multimedia data.

摘要翻译： 描述了一种用于跨多个解码器映射多个多媒体流（例如，从一组卫星转发器接收）的装置和方法。 在一个实施例中，仲裁逻辑分配多媒体流以在解码器组中（或至少等同地）平均地分解解码负载。 当系统被初始化或动态地处理流时，分配可能会静态地发生。 此外，在一个实施例中，仲裁逻辑监视存储在缓冲器中的每个流的多媒体数据的量，并且使得由具有相对更多存储的多媒体数据的解码器服务流。

公开(公告)号：US20060262885A1

公开(公告)日：2006-11-23

申请号：US11409636

申请日：2006-04-24

申请人： Eric Lais ,  Mark Greenberg ,  Manish Shah

发明人： Eric Lais ,  Mark Greenberg ,  Manish Shah

IPC分类号： H03D1/00

CPC分类号： H04L1/0052 ,  H04L1/0054 ,  H04L1/0069

摘要： An apparatus and method are described for mapping a plurality of multimedia streams (e.g., received from a set of satellite transponders) across a lesser plurality of decoders. In one embodiment, arbitration logic allocates the multimedia streams to divide the decoding load equally among the group of decoders (or at least as equally as possible). Allocation may occur statically, when the system is initialized, or dynamically, as the streams are being processed. In addition, in one embodiment, the arbitration logic monitors the amount of multimedia data for each stream stored in a buffer and causes streams to be serviced by the decoders which have relatively more stored multimedia data.

公开(公告)号：US20060101209A1

公开(公告)日：2006-05-11

申请号：US10983350

申请日：2004-11-08

申请人： Eric Lais ,  Donald DeSota ,  Rob Joersz

发明人： Eric Lais ,  Donald DeSota ,  Rob Joersz

IPC分类号： G06F13/28

CPC分类号： G06F12/082 ,  G06F2212/507

摘要： A system, method and article of manufacture for reducing latencies associated with cache coherence directory misses on external caches in a shared distributed memory data processing system. A cache coherence directory is evaluated for possible prefetching of a directory entry into a directory cache. A prefetch miss indicator is set if the prefetch evaluated results in a directory miss. The prefetch miss indicator is consulted during subsequent processing of a memory block request corresponding to the directory entry. An accelerated snoop response action is taken if the prefetch miss indicator is set. The latency of a second lookup into the cache coherence directory, which would otherwise be required, is thereby avoided.

摘要翻译： 用于减少与共享分布式存储器数据处理系统中的外部高速缓存上的高速缓存一致性目录丢失相关的延迟的系统，方法和制品。 评估缓存一致性目录可能将目录条目预取到目录缓存中。 如果预取的预取导致目录错过，则设置预取缺失指示符。 在随后处理与目录条目相对应的存储器块请求时，查阅预取缺失指示符。 如果预取缺失指示符被设置，则采取加速侦听响应动作。 从而避免了否则将要求的缓存一致性目录中的第二次查找的等待时间。

公开(公告)号：US07035355B2

公开(公告)日：2006-04-25

申请号：US09971984

申请日：2001-10-04

申请人： Eric Lais ,  Mark Greenberg ,  Manish Shah

发明人： Eric Lais ,  Mark Greenberg ,  Manish Shah

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： H04N5/4446 ,  H04N5/4401 ,  H04N5/455 ,  H04N21/4382 ,  H04N21/4383

摘要： An apparatus and method are described for mapping a plurality of multimedia streams (e.g., received from a set of satellite transponders) across a lesser plurality of decoders. In one embodiment, arbitration logic allocates the multimedia streams to divide the decoding load equally among the group of decoders (or at least as equally as possible). Allocation may occur statically, when the system is initialized, or dynamically, as the streams are being processed. In addition, in one embodiment, the arbitration logic monitors the amount of multimedia data for each stream stored in a buffer and causes streams to be serviced by the decoders which have relatively more stored multimedia data.