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    Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design
    1.
    发明授权
    Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design 失效
    准确高效地更新定时信息逻辑综合，集成电路设计布局和路由的方法

    公开(公告)号：US06449756B1

    公开(公告)日：2002-09-10

    申请号：US09094542

    申请日：1998-06-12

    申请人： Sharad Malik ,  Lawrence Pileggi ,  Eric McCaughrin ,  Abhijeet Chakraborty ,  Douglas B. Boyle

    发明人： Sharad Malik ,  Lawrence Pileggi ,  Eric McCaughrin ,  Abhijeet Chakraborty ,  Douglas B. Boyle

    IPC分类号： G06F1750

    CPC分类号： G06F17/5031

    摘要： A timing graph representing timing information of an integrated circuit design may change after modifications are made to the integrated circuit design. The modifications change timing parameters for edges in the timing graph. The measure of these changes may be computed at a computed measure compared to a threshold. In the event the measure exceeds the threshold, the edges in the timing graph that need to change in response to the modifications are updated. Otherwise, the current edges in the timing graph are continued to be used. The threshold is set in accordance with the accuracy and efficiency requirements of an electronic design automation tool.

    摘要翻译： 表示集成电路设计的定时信息的时序图可以在对集成电路设计进行修改之后改变。 修改改变时序图中边缘的时序参数。 可以在与阈值相比较的计算措施下计算这些变化的度量。 在度量超过阈值的情况下，更新需要更改的时序图中的边缘。 否则，继续使用定时图中的当前边。 阈值是根据电子设计自动化工具的精度和效率要求设定的。

    Placement method for integrated circuit design using topo-clustering
    3.
    发明授权
    Placement method for integrated circuit design using topo-clustering 失效
    使用拓扑聚类的集成电路设计的放置方法

    公开(公告)号：US06442743B1

    公开(公告)日：2002-08-27

    申请号：US09097107

    申请日：1998-06-12

    申请人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

    发明人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

    IPC分类号： G06F1750

    CPC分类号： G06F17/5072

    摘要： The disclosure describes a placement method for the physical design of integrated circuits in which natural topological feature clusters are discovered and exploited during the placement process is disclosed. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. An iterative placement refinement process is done using a technique referred to as Dual Geometrically-Bounded FM (GBFM). GBFM is applied on a local basis to windows encompassing a number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region stops participating. Following the foregoing global placement process the circuit is then ready for detailed placement in which cells are assigned to placement rows.

    摘要翻译： 本公开描述了用于集成电路的物理设计的放置方法，其中公开了在放置过程期间发现和利用自然拓扑特征簇。 拓扑群集驱动初始位置，其中所有的拓扑群集的门最初都放置在放置布局的一个bin或一组位置相关的区域中。 使用称为双重几何限幅FM（GBFM）的技术完成迭代放置细化过程。 GBFM在本地基础上应用于包含多个分区的窗口。 从迭代到迭代，窗口可能会改变位置并且大小变化。 当由窗口界定的区域在指定的成本函数方面满足指定的成本阈值时，该区域停止参与。 按照上述全局放置过程，电路准备好进行详细的放置，其中将单元格分配给放置行。

    Placement method for integrated circuit design using topo-clustering
    4.
    发明授权
    Placement method for integrated circuit design using topo-clustering 有权

    公开(公告)号：US06961916B2

    公开(公告)日：2005-11-01

    申请号：US10136161

    申请日：2002-05-01

    申请人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

    发明人： Majid Sarrafzadeh ,  Lawrence Pileggi ,  Sharad Malik ,  Feroze Peshotan Taraporevala ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Salil R. Raje ,  Lilly Shieh ,  Douglas B. Boyle ,  Dennis Yamamoto

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072

    摘要： The present invention, generally speaking, provides a placement method for the physical design of integrated circuits in which natural topological feature clusters (topo-clusters) are discovered and exploited during the placement process. Topo-clusters may be formed based on various criteria including, for example, functional similarity, proximity (in terms of number of nets), and genus. Genus refers to a representation of a netlist in terms of a number of planar netlists—netlists in which no crossing of nets occurs. Topo-clusters drive initial placement, with all of the gates of a topo-cluster being placed initially in a single bin of the placement layout or within a group of positionally-related bins. The portion of a topo-cluster placed within a given bin is called a quanto-cluster. An iterative placement refinement process then follows, using a technique referred to herein as Geometrically-Bounded FM (GBFM), and in particular Dual GBFM. In GBFM, FM is applied on a local basis to windows encompassing some number of bins. From iteration to iteration, windows may shift position and vary in size. When a region bounded by a window meets a specified cost threshold in terms of a specified cost function, that region does not participate. The cost function takes account of actual physical metrics—delay, area, congestion, power, etc. “Dual” refers to the fact that each iteration has two phases. During a first phase, FM is performed within a region on a quanto-cluster basis. During a second phase, FM is performed within the region on a gate basis. GBFM occurs in the context of recursive quadrisection. Hence, after GBFM has been completed, a further quadrisection step is performed in which each bin is divided into four bins, with a quarter of the gates of the original bin being placed in the center of each of the resulting bins. GBFM then follows, and the cycle repeats until each bin contains a fairly small number of gates. Following the foregoing global placement process, the circuit is then ready for detailed placement in which cells are assigned to placement rows.

    Method for logic optimization for improving timing and congestion during placement in integrated circuit design
    6.
    发明授权
    Method for logic optimization for improving timing and congestion during placement in integrated circuit design 失效
    用于在集成电路设计中放置时改善时序和拥塞的逻辑优化方法

    公开(公告)号：US06192508B1

    公开(公告)日：2001-02-20

    申请号：US09097076

    申请日：1998-06-12

    申请人： Sharad Malik ,  Lawrence Pileggi ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Douglas B. Boyle

    发明人： Sharad Malik ,  Lawrence Pileggi ,  Abhijeet Chakraborty ,  Gary K. Yeap ,  Douglas B. Boyle

    IPC分类号： G06F1750

    CPC分类号： G06F17/505 ,  G06F17/5072

    摘要： This invention recognizes the ability of logic optimization to help placement relieve congestion. Different types of logic optimizations are used to help placement relieve congestion. In one type of optimization, the speed of parts of the circuit is improved by selecting faster cells. In another type of optimization, the topology of the circuit is changed such that placement can now move cells, which could not have been moved before, to reduce congestion and thus enable routing. A distinguishing feature of this methodology is that it not only uses the placement information for interconnection delay/area estimates during logic optimization, but also uses logic optimization to aid the physical placement steps by providing support to placement so that the congestion of the circuit is improved. The aim is to avoid getting into a situation where the placed circuit cannot be routed.

    摘要翻译： 本发明认识到逻辑优化能够帮助放置缓解拥塞。 使用不同类型的逻辑优化来帮助放置缓解拥塞。 在一种类型的优化中，通过选择更快的单元来提高电路部分的速度。 在另一种类型的优化中，改变电路的拓扑结构，使得放置现在可以移动以前不能被移动的单元，以减少拥塞并由此实现路由。 该方法的一个突出特点是，它不仅在逻辑优化期间使用放置信息进行互连延迟/面积估计，而且还通过为放置提供支持来使用逻辑优化来辅助物理放置步骤，从而改善电路的拥塞 。 目的是避免进入放置的电路不能路由的情况。