Active matrix liquid crystal display with reduced drive pulse amplitudes
    1.
    发明授权
    Active matrix liquid crystal display with reduced drive pulse amplitudes 失效
    有源矩阵液晶显示器具有降低的驱动脉冲幅度

    公开(公告)号:US5790090A

    公开(公告)日:1998-08-04

    申请号:US730986

    申请日:1996-10-16

    IPC分类号: G09G3/36

    摘要: An active matrix liquid crystal display (AMLCD) and driving method is disclosed. The AMLCD has matrix-arranged pixel assemblies each having display electrodes. A gate line for carrying gate line pulses is connected to a control port of a row of semiconductor devices, which may be thin film transistors (TFTs). Each TFT has an output port connected to the display electrodes. In addition, a data line is connected to an input port of a column of the TFTs. A bootstrap line is capacitively connected to the display electrodes of adjacent rows. This reduce the number of bootstrap lines to half the number of gate and data lines. A bootstrap pulse timing and generating circuit is connected to the bootstrap line to provide a bootstrap pulse that shifts voltages on the display electrodes in only one direction. The bootstrap pulse has a first edge of a first polarity occurring before or during gate pulses carried on a gate line, and a second edge of a second polarity occurring after the gate line pulses.

    摘要翻译: 公开了一种有源矩阵液晶显示器(AMLCD)和驱动方法。 AMLCD具有每个具有显示电极的矩阵排列的像素组件。 用于承载栅极线脉冲的栅极线连接到一行半导体器件的控制端口,其可以是薄膜晶体管(TFT)。 每个TFT具有连接到显示电极的输出端口。 此外,数据线连接到TFT的列的输入端口。 引导线电容连接到相邻行的显示电极。 这将引导线的数量减少到门和数据线的数量的一半。 自举脉冲定时和产生电路连接到引导线,以提供自举脉冲,其仅在一个方向上移动显示电极上的电压。 自举脉冲具有第一极性的第一边缘,出现在栅极线上携带的栅极脉冲之前或之后,以及出现在栅极线脉冲之后的第二极性的第二边缘。

    Nondestructive cursors in AC plasma displays
    2.
    发明授权
    Nondestructive cursors in AC plasma displays 失效
    交流等离子体显示器中的非破坏性光标

    公开(公告)号:US4063223A

    公开(公告)日:1977-12-13

    申请号:US713567

    申请日:1976-08-11

    摘要: A nondestructive, transparent cursor for AC plasma displays may be superimposed electronically over a displayed image without regenerating the original image each time the cursor is moved. The cursor is displayed by means of a special cursor drive waveform which discharges both previously "on" and "off" cells which form the cursor but permits reversion of the cells to their original state when the cursor drive waveform is removed and the normal sustaining waveform is restored.

    摘要翻译: 用于AC等离子体显示器的非破坏性,透明的光标可以电子地叠加在所显示的图像上,而不会在每次移动光标时再生原始图像。 光标通过特殊的光标驱动波形显示,该波形对先前形成光标的“开”和“关”单元进行放电,但是当光标驱动波形被去除时允许将单元格反转到其原始状态,并且正常维持波形 被恢复。

    Writing and erasing in AC plasma displays
    3.
    发明授权
    Writing and erasing in AC plasma displays 失效
    在AC等离子显示器中写入和擦除

    公开(公告)号:US4104563A

    公开(公告)日:1978-08-01

    申请号:US845100

    申请日:1977-10-25

    IPC分类号: G09G3/28 G09G3/288 H05B41/14

    CPC分类号: G09G3/2927

    摘要: Improved writing and erasing in AC gas discharge display panels is obtained by applying a special normalizing voltage waveform to cause the cells to be in a more standardized state, so that the applied writing and erasing pulses act to cause wall voltage changes which are less sensitive to the cell's recent history. The special normalizing waveform is applied adjacent to the erase pulse and/or to the write pulse and acts to fire the cells in a manner such that there is no loss in the memory state of the cells.

    摘要翻译: 通过施加特殊的归一化电压波形来使得电池处于更加标准化的状态,从而获得改进的AC气体放电显示面板中的写入和擦除,使得所施加的写入和擦除脉冲起作用以导致对较不敏感的壁电压变化 该电池的近期历史。 特殊的归一化波形与擦除脉冲和/或写入脉冲相邻地施加,并且以使得单元的存储器状态没有损失的方式起作用。

    Distributed Josephson junction logic circuit
    4.
    发明授权
    Distributed Josephson junction logic circuit 失效
    分布式JOSEPHSON JUNCTION LOGIC CIRCUIT

    公开(公告)号:US4039856A

    公开(公告)日:1977-08-02

    申请号:US636868

    申请日:1975-12-02

    IPC分类号: H03K19/177 H03K19/195

    摘要: A distributed Josephson junction logic circuit is disclosed which includes a plurality of serially disposed Josephson junctions in a superconductive wire-over-groundplane environment wherein the latter is terminated at both ends in its characteristic impedance and energized at one end with a constant voltage source. In addition, at least one portion of the wire-over-groundplane transmission line, which is disposed in series with the junctions, is utilized as an output control and has the same steady state current flowing in it as the plurality of Josephson junctions. Utilizing such an arrangement, logic can be performed by means of multiple controls on a single junction as in terminated line logic or by means of several junctions, each with one or more independent controls, in series. The design is such that the switching of any one or more junctions to the voltage state causes a decrease in current from a level which represents a logical "1" to a lesser current which is representative of a logical "0". The resulting logic circuits may be latching or non-latching in character. When both ends of the distributed Josephson junction logic circuit are terminated in the characteristic impedance of the associated transmission line, inputs and outputs can be located at arbitrary points along the transmission line. The terminating resistors, returned at both ends of the line to points of low impedance to ground compared to the impedance of the terminating resistor, absorb transients originating on the power line or at any point along the transmission line. When any one or more of the inputs to such a circuit is a logical "1", at least one of the associated gates switches to the voltage state, reducing the output current to the logical "0" level. In a latching mode of operation, the circuit latches in that state until the gate current is momentarily quenched by reducing the power supply voltage. Thus, each stage normally inverts. The logic operation performed is a positive NOR, which is sufficient to implement any logical function. If desired, two or three controls can be used with some or all of the gates to perform such functions as inhibit, AND-OR-INVERT and majority and threshold logic. Logic circuits utilizing Josephson junctions operating at the gap which provide constant voltages are shown. In addition, circuit arrangements incorporating series-parallel powering circuits and the interconnection of logic circuits between more than one circuit arrangement are shown.