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    Communications in a processor array
    1.
    发明申请
    Communications in a processor array 有权
    处理器阵列中的通信

    公开(公告)号：US20070083791A1

    公开(公告)日：2007-04-12

    申请号：US10546616

    申请日：2004-02-19

    申请人： Gajinder Panesar ,  Anthony Claydon ,  William Robbins ,  Alex Orr ,  Andrew Duller

    发明人： Gajinder Panesar ,  Anthony Claydon ,  William Robbins ,  Alex Orr ,  Andrew Duller

    IPC分类号： G06F11/00

    CPC分类号： G06F13/4286

    摘要： Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.

    摘要翻译： 在所分配的时隙期间，数据从发送处理器通过网络传送到一个或多个接收处理器，并且在相同的分配时隙期间以相反的方向发送确认信号，以指示接收处理器是否能够接收 数据如果一个或多个接收处理器指示它不能接收数据，则在下一个分配的时隙期间重传该数据。 这意味着发送处理器能够在时隙周期内确定是否需要重传，但是时隙周期只需要足够长以进行单向通信。

    Communications in a processor array
    2.
    发明授权
    Communications in a processor array 有权
    处理器阵列中的通信

    公开(公告)号：US07987340B2

    公开(公告)日：2011-07-26

    申请号：US10546616

    申请日：2004-02-19

    申请人： Gajinder Panesar ,  Anthony Peter John Claydon ,  William Philip Robbins ,  Alex Orr ,  Andrew Duller

    发明人： Gajinder Panesar ,  Anthony Peter John Claydon ,  William Philip Robbins ,  Alex Orr ,  Andrew Duller

    IPC分类号： G06F15/80

    CPC分类号： G06F13/4286

    摘要： Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.

    摘要翻译： 在所分配的时隙期间，数据从发送处理器通过网络传送到一个或多个接收处理器，并且在相同的分配时隙期间以相反的方向发送确认信号，以指示接收处理器是否能够接收 数据如果一个或多个接收处理器指示它不能接收数据，则在下一个分配的时隙期间重传该数据。 这意味着发送处理器能够在时隙周期内确定是否需要重传，但是时隙周期只需要足够长以进行单向通信。

    Processor architecture
    4.
    发明申请
    Processor architecture 审中-公开
    处理器架构

    公开(公告)号：US20060155958A1

    公开(公告)日：2006-07-13

    申请号：US11293845

    申请日：2005-12-02

    申请人： Andrew Duller ,  Gajinder Panesar ,  Peter Claydon ,  William Robbins ,  Andrew Kuligowski ,  Olfat Younis

    发明人： Andrew Duller ,  Gajinder Panesar ,  Peter Claydon ,  William Robbins ,  Andrew Kuligowski ,  Olfat Younis

    IPC分类号： G06F15/00

    CPC分类号： G06F9/3885 ,  G06F9/30149 ,  G06F9/3853 ,  G06F9/3891

    摘要： A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor, because it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously. These execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device. An array is formed from multiple interconnected processors of this type.

    摘要翻译： LIW处理器包括多个执行单元。 处理器的多个执行单元被分成组，并且输入指令字可以包含每个组中的一个执行单元的指令。 处理器被优化用于信号处理操作，因为处理器的多个执行单元被划分成不对处理器的期望使用施加显着限制的组，因为已经确定在信号处理应用中， 某些执行单元通常不需要同时操作。 因此，这些执行单元可以被组合在一起，使得它们中只有一个可以在特定时间操作，而不会显着影响设备的操作。 由这种类型的多个互连的处理器形成阵列。

    Processor Architecture
    6.
    发明申请
    Processor Architecture 有权
    处理器架构

    公开(公告)号：US20080065859A1

    公开(公告)日：2008-03-13

    申请号：US11981973

    申请日：2007-11-01

    申请人： Andrew Duller ,  Gajinder Panesar ,  Peter Claydon ,  William Robbins ,  Andrew Kuligowski ,  Olfat Younis

    发明人： Andrew Duller ,  Gajinder Panesar ,  Peter Claydon ,  William Robbins ,  Andrew Kuligowski ,  Olfat Younis

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3885 ,  G06F9/30149 ,  G06F9/3853 ,  G06F9/3891

    摘要： A LIW processor comprises multiple execution units. The multiple execution units of the processor are divided into groups, and an input instruction word can contain instructions for one execution unit in each of the groups. The processor is optimised for use in signal processing operations, in that the multiple execution units of the processor are divided into groups which do not place significant restrictions on the desirable uses of the processor, because it has been determined that, in signal processing applications, it is not usually necessary for certain execution units to operate simultaneously. These execution units can therefore be grouped together, in such a way that only one of them can operate at a particular time, without significantly impacting on the operation of the device. An array is formed from multiple interconnected processors of this type.

    摘要翻译： LIW处理器包括多个执行单元。 处理器的多个执行单元被分成组，并且输入指令字可以包含每个组中的一个执行单元的指令。 处理器被优化用于信号处理操作，因为处理器的多个执行单元被划分成不对处理器的期望使用施加显着限制的组，因为已经确定在信号处理应用中， 某些执行单元通常不需要同时操作。 因此，这些执行单元可以被组合在一起，使得它们中只有一个可以在特定时间操作，而不会显着影响设备的操作。 由这种类型的多个互连的处理器形成阵列。