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公开(公告)号：US20070220232A1
公开(公告)日：2007-09-20
申请号：US11752299
申请日：2007-05-23
申请人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
发明人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
IPC分类号： G06F15/00
CPC分类号： H04L45/00 , G06F1/10 , G06F15/8007 , G06F17/505 , H04L12/56 , H04L45/742 , Y10S707/99936
摘要： A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
摘要翻译： 一种数据处理架构，包括：用于接收数据分组的输入流的输入装置; 以及可操作以处理由此接收的数据的多个处理元件; 其中所述输入设备可操作以根据所述处理元件的数据处理带宽将数据分组全部或部分地分配给所述处理单元。
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2.发明授权SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream 有权SIMD阵列可操作以在执行单个公共指令流的同时处理不同的相应分组协议公开(公告)号：US08127112B2
公开(公告)日：2012-02-28
申请号：US12965673
申请日：2010-12-10
申请人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
发明人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
IPC分类号： G06F15/16
CPC分类号： H04L45/00 , G06F1/10 , G06F15/8007 , G06F17/505 , H04L12/56 , H04L45/742 , Y10S707/99936
摘要： A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
摘要翻译： 数据处理架构包括接收数据分组的输入流的输入设备。 多个处理元件可操作以处理从输入设备接收的数据。 输入设备可操作以根据处理元件的数据处理带宽将数据分组全部或部分地分配给处理元件。
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3.发明授权公开(公告)号：US07917727B2
公开(公告)日：2011-03-29
申请号：US11752300
申请日：2007-05-23
申请人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
发明人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
IPC分类号： G06F15/16
CPC分类号： H04L45/00 , G06F1/10 , G06F15/8007 , G06F17/505 , H04L12/56 , H04L45/742 , Y10S707/99936
摘要： An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in the array under the control of the PEs. Transfer to or from the array may be carried out when either a batch or part of a batch is ready for transfer. The decision to transfer either full or part batches is made in dependence upon the speed of the PEs and the speed and intermittency of the data packets.
摘要翻译： 输入/输出系统将数据分组传送到SIMD阵列的处理元件（PE），从而将不同大小的数据分组传送到相应的PE。 分组在PE的控制下分批传送到阵列中各自的不同地址。 当批次或批次的一部分准备好进行传输时，可以将数据传输到阵列或从阵列传输。 根据PE的速度和数据包的速度和间歇性，进行全部或部分批次的转移决定。
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4.发明授权Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream 有权用于分组处理的数据处理体系结构，其中批量的不可预测大小的数据分组分布在布置在SIMD阵列中的处理元件之间，可操作以同时执行单个公共指令流来同时处理不同的相应分组协议公开(公告)号：US07856543B2
公开(公告)日：2010-12-21
申请号：US10073948
申请日：2002-02-14
申请人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
发明人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
IPC分类号： G06F15/80
CPC分类号： H04L45/00 , G06F1/10 , G06F15/8007 , G06F17/505 , H04L12/56 , H04L45/742 , Y10S707/99936
摘要： A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
摘要翻译： 一种数据处理架构，包括：用于接收数据分组的输入流的输入装置; 以及可操作以处理由此接收的数据的多个处理元件; 其中所述输入设备可操作以根据所述处理元件的数据处理带宽将数据分组全部或部分地分配给所述处理单元。
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公开(公告)号：US07818541B2
公开(公告)日：2010-10-19
申请号：US11752299
申请日：2007-05-23
申请人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
发明人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
CPC分类号： H04L45/00 , G06F1/10 , G06F15/8007 , G06F17/505 , H04L12/56 , H04L45/742 , Y10S707/99936
摘要： A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
摘要翻译： 一种数据处理架构，包括：用于接收数据分组的输入流的输入装置; 以及可操作以处理由此接收的数据的多个处理元件; 其中所述输入设备可操作以根据所述处理元件的数据处理带宽将数据分组全部或部分地分配给所述处理单元。
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公开(公告)号：US20070217453A1
公开(公告)日：2007-09-20
申请号：US11752300
申请日：2007-05-23
申请人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
发明人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
IPC分类号： H04J3/06
CPC分类号： H04L45/00 , G06F1/10 , G06F15/8007 , G06F17/505 , H04L12/56 , H04L45/742 , Y10S707/99936
摘要： A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
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公开(公告)号：US06324632B1
公开(公告)日：2001-11-27
申请号：US09223827
申请日：1998-12-30
申请人： Simon McIntosh-Smith
发明人： Simon McIntosh-Smith
IPC分类号： G06F1214
CPC分类号： G06F12/0848 , G06F12/0842 , Y10T74/1519 , Y10T74/1531
摘要： A method and computer for processing an incoming data stream, for example of video or audio data is described. A system memory is divided into first and second memory spaces, the first memory space for holding a data stream and the second memory space for holding a set of program data. A cache has first and second partitions allocated exclusively respectively to the first and second memory spaces. In this manner, when the data stream is transferred between an execution unit and the main memory, program data is not evicted from the cache.
摘要翻译： 描述了用于处理输入数据流的方法和计算机，例如视频或音频数据。 系统存储器被分为第一和第二存储器空间，用于保存数据流的第一存储器空间和用于保存一组程序数据的第二存储器空间。 高速缓存具有分配给第一和第二存储器空间的第一和第二分区。 以这种方式，当数据流在执行单元和主存储器之间传送时，程序数据不会从高速缓存中逐出。
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公开(公告)号：US20110083000A1
公开(公告)日：2011-04-07
申请号：US12965673
申请日：2010-12-10
申请人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
发明人： John Rhoades , Ken Cameron , Paul Winser , Ray McConnell , Gordon Faulds , Simon McIntosh-Smith , Anthony Spencer , Jeff Bond , Matthias Dejaegher , Danny Halamish , Gajinder Panesar
CPC分类号： H04L45/00 , G06F1/10 , G06F15/8007 , G06F17/505 , H04L12/56 , H04L45/742 , Y10S707/99936
摘要： A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.
摘要翻译： 数据处理架构包括接收数据分组的输入流的输入设备。 多个处理元件可操作以处理从输入设备接收的数据。 输入设备可操作以根据处理元件的数据处理带宽将数据分组全部或部分地分配给处理元件。
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