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    Entry level data processing system which is expandable by a factor of two to a partitionable upgraded system with low overhead
    1.
    发明授权
    Entry level data processing system which is expandable by a factor of two to a partitionable upgraded system with low overhead 失效
    入门级数据处理系统，其可扩展为二分之一到具有低开销的可分层升级系统

    公开(公告)号：US5446848A

    公开(公告)日：1995-08-29

    申请号：US82175

    申请日：1993-06-25

    申请人： Gary C. Whitlock ,  Richard D. Freeman ,  Keith S. Saldanha

    发明人： Gary C. Whitlock ,  Richard D. Freeman ,  Keith S. Saldanha

    IPC分类号： G06F13/40 ,  G06F11/20

    CPC分类号： G06F13/4027 ,  G06F13/4068

    摘要： An entry level data processing system is expandable, with low overhead, by a factor of two to a partitionable upgraded data processing system. This entry level system includes: 1) one system bus, 2) a central processing module (CPM), an input/output module (IOM), and a system control module (SCM)--all of which have one system bus port coupled to the system bus, 3) a memory module coupled via a memory bus to the system control module, and 4) a system expansion interface through which the entry level system is expanded to the upgraded system. In one particular preferred embodiment, the system expansion interface consists of a) a first connector on the SCM for externally connecting to and communicating with the memory bus, b) a second connector on the SCM for externally connecting to and communicating with the system bus, and c) an extension of the system bus through a switch in the SCM and a third connector on the SCM for externally connecting to and communicating with the extended system bus. To expand the entry level system to the upgraded system, a duplicate copy of the entry level data processing system as recited in 1-4 above is added along with a respective three port bus expansion module (BEM) in each copy of the entry level data processing system. This BEM, in each particular entry level system, intercouples the first and second connectors on the SCM of that same system to the third connector on the SCM of the other entry level system.

    摘要翻译： 入门级数据处理系统可扩展，具有较低的开销，可扩展到可分区的升级数据处理系统的两倍。 该入门级系统包括：1）一个系统总线，2）中央处理模块（CPM），输入/输出模块（IOM）和系统控制模块（SCM），其中一个系统总线端口耦合到 系统总线，3）通过存储器总线耦合到系统控制模块的存储器模块，以及4）系统扩展接口，通过该系统扩展接口将入门级系统扩展到升级系统。 在一个特定的优选实施例中，系统扩展接口包括：a）SCM上的第一连接器，用于外部连接到存储器总线并与存储器总线通信; b）SCM上的第二连接器，用于外部连接到系统总线并与系统总线通信; 以及c）通过SCM中的开关和SCM上的第三个连接器来扩展系统总线，用于外部连接到扩展系统总线并与其通信。 为了将入门级系统扩展到升级的系统，将上述1-4中所述的入门级数据处理系统的副本与各入口级数据的每个副本中的相应的三端口总线扩展模块（BEM）一起被添加 处理系统。 该BEM在每个特定的入门级系统中将该同一系统的SCM上的第一个和第二个连接器互连到另一个入门级系统的SCM上的第三个连接器。

    Error log system for self-testing in very large scale integrated circuit (VLSI) units
    2.
    发明授权
    Error log system for self-testing in very large scale integrated circuit (VLSI) units 失效
    用于大规模集成电路（VLSI）单元自检的错误日志系统

    公开(公告)号：US4932028A

    公开(公告)日：1990-06-05

    申请号：US209664

    申请日：1988-06-21

    申请人： Haluk Katircioglu ,  John A. De Beule ,  Debaditya Mukherjee ,  Gary C. Whitlock

    发明人： Haluk Katircioglu ,  John A. De Beule ,  Debaditya Mukherjee ,  Gary C. Whitlock

    IPC分类号： G06F11/07 ,  G06F11/32

    CPC分类号： G06F11/0772 ,  G06F11/32

    摘要： A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED). If a fatal error is detected (one which would destroy the reliability of chip operations), then the chip is immobilized into a hold mode (freeze). Interrupts are signalled to a cooperating maintenance controller which can pass the error information to an external computer for display and for locating a faulty area.

    摘要翻译： VSLI芯片采用寄存器实现，该寄存器记录由并发错误检测电路（CED）感测到的芯片内发生的永久性和间歇性错误。 如果检测到致命错误（将破坏芯片操作的可靠性），则芯片被固定为保持模式（冻结）。 信号通知给协调维护控制器的中断可以将错误信息传递给外部计算机进行显示和定位故障区域。