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公开(公告)号：US5764096A
公开(公告)日：1998-06-09
申请号：US754116
申请日：1996-11-21
IPC分类号： G11C16/04 , H03K19/173 , G11C11/34
CPC分类号： H03K19/1736 , G11C16/0441
摘要： A programmable interconnect which closely integrates an independent switching transistor with separate NVM programming and erasing elements. The programming element is an EPROM transistor and the erasing element is a Fowler-Nordheim tunneling device. A unitary floating gate is shared by the switching transistor and the NVM programming and elements which charge and discharge the floating gate. The shared floating gate structure is the memory structure of the integrated programmable interconnect and controls the impedance of the switching transistor.
摘要翻译： 一个可编程互连，将独立的开关晶体管与独立的NVM编程和擦除元件紧密集成。 编程元件是EPROM晶体管，擦除元件是Fowler-Nordheim隧穿器件。 一个单一的浮动栅极由开关晶体管和NVM编程和对浮动栅极充电和放电的元件共享。 共享浮栅结构是集成可编程互连的存储器结构，并控制开关晶体管的阻抗。
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2.发明授权
公开(公告)号：US5594363A
公开(公告)日：1997-01-14
申请号：US418972
申请日：1995-04-07
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704
摘要： The present invention provides for an FPGA integrated circuit having an array of logic cells and interconnect lines interconnected by programmable switches, each formed from a nonvolatile memory cell. The logic cell is designed to provide logic or memory functions according to the setting of programmable switches within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between the wiring segments.
摘要翻译： 本发明提供了一种FPGA集成电路，其具有由非易失性存储单元形成的可编程开关互连的逻辑单元和互连线阵列。 逻辑单元被设计为根据单元内的可编程开关的设置来提供逻辑或存储器功能。 阵列中的逻辑单元可通过本地，长和全局布线段的层次结构互连。 互连通过布线段之间的可编程开关的设置来实现。
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3.发明授权Solid state key for controlling access to computer systems and to computer software and/or for secure communications 失效用于控制对计算机系统和计算机软件的访问和/或用于安全通信的固态密钥
公开(公告)号：US4819267A
公开(公告)日：1989-04-04
申请号：US62322
申请日：1987-06-09
CPC分类号： G07F7/1008 , G06F21/34 , G07C9/00015 , G07C9/00023 , G07C9/00039 , G07F7/1025 , G06F2211/007 , G06F2221/2103 , G07C2009/00785
摘要： A semiconductor device that functions as a key to control access to a computer or a software program resident in a computer or provides for secure communications is disclosed. The device executes an algorithm that combines a root and a seed to produce a password. The password is input to the computer. The computer uses an equivalent algorithm to produce a password within the computer. Comparison or other methods are employed to allow access to the computer or computer program or to allow for secure communications. The computer can be coded to produce on a video display thereof a time-space stimulus pattern which can be received by sensors of the key. Alternatively, a keypad can be employed to input the stimulus output from the computer into the access key. Further the present system allows for secure communication using algorithms between different computers and between distant locations.
摘要翻译： 公开了用作控制对计算机或驻留在计算机中的软件程序的访问或提供安全通信的键的半导体器件。 该设备执行组合根和种子以生成密码的算法。 密码输入到计算机。 计算机使用等效的算法在计算机内产生密码。 采用比较或其他方法来允许访问计算机或计算机程序或允许安全通信。 计算机可以被编码以在其视频显示器上产生可由密钥的传感器接收的时空刺激图案。 或者，可以使用小键盘将从计算机输出的刺激输入到访问键。 此外，本系统允许使用不同计算机之间和远程位置之间的算法的安全通信。
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4.发明授权Determining timing paths within a circuit block of a programmable integrated circuit 有权确定可编程集成电路的电路块内的定时路径公开(公告)号：US08117577B1
公开(公告)日：2012-02-14
申请号：US12361516
申请日：2009-01-28
申请人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
发明人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
CPC分类号： G06F17/5054 , G06F17/5031 , G06F2217/84
摘要： A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.
摘要翻译： 识别电路块的定时路径的计算机实现的方法可以包括表示包括至少一个可旁路组件的电路块作为具有由节点链接的多个元件的框图。 该方法可以包括生成包括框图中每个元素的文本描述的地图文件，其中每个元素的文本描述指定该元素的旁路指示符。 该方法还可以包括从地图文件生成多个子路径，根据多个子路径的起始点和终点的共同点选择性地组合多个子路径中的不同子路径，从多个子路径确定定时路径 多个子路径，并输出定时路径。
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公开(公告)号：US5214512A
公开(公告)日：1993-05-25
申请号：US654540
申请日：1991-02-11
申请人： Richard D. Freeman
发明人： Richard D. Freeman
摘要： A keyed, true-transparency combine and keyer receive prioritized image information signals and their corresponding input key signals. On the one hand, others have changed the order of the channels carrying the image signals as the priority of the image signals changes. On the other hand, here we interchange the order of a plurality of substantially identical keyer units within a keyer as the priority of the image signals changes. In interchanging the keyer units, true transparency processed key signals are also generated. In so doing that, the i-th keyer unit modifies the value of its input key signal Bk.sub.i using values of input key signals from higher priority channels. Thereby a true transparency processed key signal Pk.sub.i is generated for the i-th priority channel. In one embodiment, a key-taken signal is generated by multiplying a key-requested signal and a key-available signal while a key-now-available signal is generated by subtracting the key-taken signal from the key-available signal. In another embodiment, a key-taken signal is generated by subtracting a key-now-available signal from a key-available signal while a key-now-available signal is generated by multiplying the key-available signal by one minus the key-requested signal. In either embodiment, the generated key-now-available signal from a higher priority i-th channel is provided to a lower priority (i+1)-st channel as the key-available signal for the lower priority channel and the processed key signal Pk.sub.i is generated in response to the key-taken signal.
摘要翻译： 键控的真实透明度组合和键控器接收优先级图像信息信号及其相应的输入键信号。 一方面，随着图像信号的优先级的变化，其他人改变了携带图像信号的频道的顺序。 另一方面，这里，随着图像信号的优先级的改变，在键控器内交换多个基本相同的键控单元的顺序。 在交换键控单元时，也会产生真正的透明度处理键信号。 这样做，第i个键控单元使用来自较高优先级信道的输入键信号的值来修改其输入键信号Bki的值。 因此，为第i个优先级信道生成真实的透明度处理密钥信号Pki。 在一个实施例中，通过将密钥请求的信号和密钥可用信号相乘来生成密钥获取信号，同时通过从密钥可用信号中减去获取密钥的信号来产生密钥现在可用信号。 在另一个实施例中，通过从密钥可用信号中减去密钥现在可用信号来产生密钥获取信号，同时通过将密钥可用信号乘以减去密钥请求的一个密钥可用信号而产生密钥现在可用信号 信号。 在任一实施例中，来自较高优先级的第i个信道的生成的密钥现在可用的信号被提供给较低优先级（i + 1）信道，作为较低优先级信道的密钥可用信号和经处理的密钥信号 响应于按键信号产生Pki。
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公开(公告)号：US4195338A
公开(公告)日：1980-03-25
申请号：US35025
申请日：1970-05-06
申请人： Richard D. Freeman
发明人： Richard D. Freeman
CPC分类号： G09G5/24
摘要： Apparatus and methods are disclosed for defining and controlling the relative positioning of symbols in a computer-based imaging system for generating images suitable for controlling a printing operation. Information describing the symbols is stored in a memory and is retrieved and the corresponding symbol relatively positioned on an imaging device in response to a control program and an input specification of the desired coincidence of "concatenation points" associated with each symbol.
摘要翻译： 公开了用于定义和控制基于计算机的成像系统中的符号的相对定位的装置和方法，用于产生适于控制打印操作的图像。 描述符号的信息被存储在存储器中，并且响应于与每个符号相关联的“级联点”的控制程序和期望的重合的输入规范，被检索并相应地位于成像设备上的相应符号。
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7.发明授权Single chip processing system utilizing general cache and microcode cache enabling simultaneous multiple functions 失效单芯片处理系统采用通用缓存和微码高速缓存，实现同时多功能
公开(公告)号：US5634108A
公开(公告)日：1997-05-27
申请号：US674408
申请日：1996-07-02
申请人： Richard D. Freeman
发明人： Richard D. Freeman
CPC分类号： G06F12/123 , G06F12/0875 , G06F12/0891 , G06F2212/453
摘要： A microcode cache memory is provided on a processor chip for supplying frequently used microcode instruction words to a processor. A bank of multiple Tag-Status RAMs holds addresses of microcode words residing in a bank of Data RAMs. A state machine and a special Least Recently Used Random Access Memory (LRU RAM) operate to maintain the more frequently used words in the Data RAMs so that more hits occur to provide the requested word in one clock cycle. A 90 bit microcode word with 20 fields enables the processor to perform multiple functions simultaneously in parallel.
摘要翻译： 在处理器芯片上提供微代码高速缓冲存储器，用于将经常使用的微代码指令字提供给处理器。 多个标签状态RAM的存储体保存驻留在数据RAM组中的微码字的地址。 状态机和特殊的最近使用的随机存取存储器（LRU RAM）用于在数据RAM中维持更频繁使用的字，以便在一个时钟周期内提供更多的命中以提供所请求的字。 具有20个字段的90位微码字使处理器能够并行同时执行多个功能。
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公开(公告)号：US5594698A
公开(公告)日：1997-01-14
申请号：US334885
申请日：1994-11-04
申请人： Richard D. Freeman
发明人： Richard D. Freeman
IPC分类号： G11C7/10 , G11C11/406 , H03K19/177 , G11C7/00
CPC分类号： H03K19/177 , G11C11/406 , G11C7/1006 , H03K19/17704
摘要： A field programmable device includes two separate and electrically isolated arrays of rows and columns of conductors sharing the same area of an integrated circuit substrate, one array interconnecting memory cells to form a random access memory ("RAM"). The other array forms a full or partial cross-point switching network that is controlled by information stored in memory cells, and/or connects to an operating electronic circuit that is configurable and operable in accordance with information stored in memory cells. In addition, the memory array is easily used to access desired nodes of the circuit array in order to be able to easily observe internal signals during operation. A preferred memory structure is a dynamic random access memory ("DRAM") because of a high density and low cost of existing DRAM fabrication techniques, even though periodic reading and refreshing of the states of the memory cells is required. Several circuits and techniques are used which allow continuous assertion of the memory cell states without interruption during the their refreshing cycles.
摘要翻译： 现场可编程器件包括两个独立且电隔离的行和列的列，这些阵列与集成电路衬底的相同区域共享，一个阵列互连存储器单元以形成随机存取存储器（“RAM”）。 另一阵列形成由存储在存储器单元中的信息控制的全部或部分交叉点交换网络，和/或连接到根据存储在存储单元中的信息可配置和可操作的操作电子电路。 此外，存储器阵列易于用于访问电路阵列的所需节点，以便能够在操作期间容易地观察内部信号。 优选的存储器结构是动态随机存取存储器（“DRAM”），因为现有DRAM制造技术具有高密度和低成本，即使需要定期读取和刷新存储器单元的状态。 使用几种电路和技术，其允许在其刷新周期期间不间断地连续断言存储器单元状态。
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公开(公告)号：USD368680S
公开(公告)日：1996-04-09
申请号：US34194
申请日：1995-01-30
申请人： Richard D. Freeman
设计人： Richard D. Freeman
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10.发明授权Entry level data processing system which is expandable by a factor of two to a partitionable upgraded system with low overhead 失效入门级数据处理系统，其可扩展为二分之一到具有低开销的可分层升级系统
公开(公告)号：US5446848A
公开(公告)日：1995-08-29
申请号：US82175
申请日：1993-06-25
CPC分类号： G06F13/4027 , G06F13/4068
摘要： An entry level data processing system is expandable, with low overhead, by a factor of two to a partitionable upgraded data processing system. This entry level system includes: 1) one system bus, 2) a central processing module (CPM), an input/output module (IOM), and a system control module (SCM)--all of which have one system bus port coupled to the system bus, 3) a memory module coupled via a memory bus to the system control module, and 4) a system expansion interface through which the entry level system is expanded to the upgraded system. In one particular preferred embodiment, the system expansion interface consists of a) a first connector on the SCM for externally connecting to and communicating with the memory bus, b) a second connector on the SCM for externally connecting to and communicating with the system bus, and c) an extension of the system bus through a switch in the SCM and a third connector on the SCM for externally connecting to and communicating with the extended system bus. To expand the entry level system to the upgraded system, a duplicate copy of the entry level data processing system as recited in 1-4 above is added along with a respective three port bus expansion module (BEM) in each copy of the entry level data processing system. This BEM, in each particular entry level system, intercouples the first and second connectors on the SCM of that same system to the third connector on the SCM of the other entry level system.
摘要翻译： 入门级数据处理系统可扩展，具有较低的开销，可扩展到可分区的升级数据处理系统的两倍。 该入门级系统包括：1）一个系统总线，2）中央处理模块（CPM），输入/输出模块（IOM）和系统控制模块（SCM），其中一个系统总线端口耦合到 系统总线，3）通过存储器总线耦合到系统控制模块的存储器模块，以及4）系统扩展接口，通过该系统扩展接口将入门级系统扩展到升级系统。 在一个特定的优选实施例中，系统扩展接口包括：a）SCM上的第一连接器，用于外部连接到存储器总线并与存储器总线通信; b）SCM上的第二连接器，用于外部连接到系统总线并与系统总线通信; 以及c）通过SCM中的开关和SCM上的第三个连接器来扩展系统总线，用于外部连接到扩展系统总线并与其通信。 为了将入门级系统扩展到升级的系统，将上述1-4中所述的入门级数据处理系统的副本与各入口级数据的每个副本中的相应的三端口总线扩展模块（BEM）一起被添加 处理系统。 该BEM在每个特定的入门级系统中将该同一系统的SCM上的第一个和第二个连接器互连到另一个入门级系统的SCM上的第三个连接器。
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