公开(公告)号：US07254652B2

公开(公告)日：2007-08-07

申请号：US10675678

申请日：2003-09-30

申请人： Gary Dean Anderson ,  David Alan Bailey ,  Peter Rudolf Keller ,  Diane Lacey Knipfer

发明人： Gary Dean Anderson ,  David Alan Bailey ,  Peter Rudolf Keller ,  Diane Lacey Knipfer

IPC分类号： G06F13/00 ,  G06F15/177

CPC分类号： G06F13/4072 ,  H04L5/1446

摘要： The present invention provides a method and computer program product for reading an encoded cable speed/length value contained within an interconnection cable to set the interconnection speed of two or more components connected by the interconnection cable within a computing environment. This method detects changes to the cable connections within the I/O fabric of the computing environment, and autonomically reconfigures the connected components to enable the interconnected devices to communicate at the maximum effective bandwidth, based on the length of the interconnection cables utilized.

摘要翻译： 本发明提供了一种用于读取互连电缆中包含的编码电缆速度/长度值的方法和计算机程序产品，以在计算环境内设置由互连电缆连接的两个或多个组件的互连速度。 该方法检测对计算环境的I / O结构内的电缆连接的改变，并且基于所使用的互连电缆的长度，自主地重新配置所连接的组件以使得互连设备能够以最大有效带宽进行通信。

公开(公告)号：US07536493B2

公开(公告)日：2009-05-19

申请号：US11279436

申请日：2006-04-12

申请人： Gary Dean Anderson ,  Joseph Donald Armstrong ,  Brent William Jacobs ,  Ajay Kumar Mahajan

发明人： Gary Dean Anderson ,  Joseph Donald Armstrong ,  Brent William Jacobs ,  Ajay Kumar Mahajan

IPC分类号： G06F13/14

CPC分类号： G06F21/31 ,  G06F21/71 ,  G06F21/73 ,  G06F2221/2129

摘要： The aspects of the present invention provide a computer implemented method, an apparatus, and a computer usable program code for identifying a service processor with current setting information. First stored information for a service processor is retrieved from a first memory in the first service processor. Second stored information for the service processor is retrieved from a second memory in a data processing system to which the service processor is connected. The first stored information is compared with the second stored information to form a comparison as to whether the service processor was previously connected to the data processing system and to determine whether the service processor was a last service processor to fully communicate with system firmware in the data processing system. The service processor has current setting information if the service processor was previously connected to the data processing system and was the last service processor to fully communicate with the system firmware.

摘要翻译： 本发明的方面提供了一种计算机实现的方法，装置和用于使用当前设置信息识别服务处理器的计算机可用程序代码。 从第一服务处理器中的第一存储器检索用于服务处理器的第一存储信息。 从与服务处理器连接的数据处理系统中的第二存储器检索用于服务处理器的第二存储信息。 将第一存储信息与第二存储信息进行比较以形成关于服务处理器是否先前连接到数据处理系统并且确定服务处理器是否是最后服务处理器以与数据中的系统固件完全通信的比较 处理系统。 如果服务处理器先前连接到数据处理系统，并且是与系统固件完全通信的最后一个服务处理器，则服务处理器具有当前设置信息。

公开(公告)号：US07886192B2

公开(公告)日：2011-02-08

申请号：US12165058

申请日：2008-06-30

申请人： Gary Dean Anderson ,  Sheldon Ray Bailey ,  Wayne Allan Britson ,  Alongkorn Kitamorn ,  Michael Alan Kobler

发明人： Gary Dean Anderson ,  Sheldon Ray Bailey ,  Wayne Allan Britson ,  Alongkorn Kitamorn ,  Michael Alan Kobler

IPC分类号： G06F11/00

CPC分类号： G06F11/1417 ,  G06F9/4401 ,  G06F11/1482

摘要： A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process.

摘要翻译： 用于快速系统恢复的系统和方法，通过在重新启动之前断开系统中的故障硬件，从而绕过诊断程序。 被系统故障硬件拆除影响的硬件和硬件故障将与系统断开连接。 系统重新启动，并且由于发生故障的硬件已断开连接，诊断程序可能会安全地从重启过程中消除。

公开(公告)号：US07657730B2

公开(公告)日：2010-02-02

申请号：US11456102

申请日：2006-07-07

申请人： Salim Ahmed Agha ,  Gary Dean Anderson ,  Wayne Allan Britson ,  Brent William Jacobs ,  William Thomas Truskowski

发明人： Salim Ahmed Agha ,  Gary Dean Anderson ,  Wayne Allan Britson ,  Brent William Jacobs ,  William Thomas Truskowski

IPC分类号： G06F9/00 ,  G06F9/24 ,  G06F15/177

CPC分类号： G06F11/0754 ,  G06F11/0751

摘要： In response to the start of an initialization sequence at a service processor, if power to a main processor was interrupted at a most-recent time that an operating system executed on the main processor, power to the main processor is turned on, the operating system is started executing on the main processor, data from the non-volatile memory of the service processor is provided to the operating system, and the service processor is reset, which restarts the initialization sequence. If the power to the main processor was not interrupted at the most-recent time that the operating system executed on the main processor, and if the operating system is currently executing on the main processor, a monitoring function is started in the service processor, which monitors for errors at a computer system.

摘要翻译： 响应于在服务处理器处的初始化序列的开始，如果在主处理器上执行的操作系统的主要处理器的电源被接通，则主处理器的电力在最近的时间被中断，则操作系统 在主处理器上开始执行，来自服务处理器的非易失性存储器的数据被提供给操作系统，并且服务处理器被重置，其重新启动初始化序列。 如果主处理器的电源在最近的操作系统在主处理器上执行的时间没有中断，如果操作系统当前正在主处理器上执行，则在服务处​​理器中启动监视功能， 监视计算机系统的错误。

公开(公告)号：US06338119B1

公开(公告)日：2002-01-08

申请号：US09282631

申请日：1999-03-31

申请人： Gary Dean Anderson ,  Ronald Xavier Arroyo ,  Bradly George Frey ,  Guy Lynn Guthrie

发明人： Gary Dean Anderson ,  Ronald Xavier Arroyo ,  Bradly George Frey ,  Guy Lynn Guthrie

IPC分类号： G06F1300

CPC分类号： G06F12/0835 ,  G06F13/28

摘要： A method and apparatus for improving direct memory access and cache performance utilizing a special Input/Output or “I/O” page, defined as having a large size (e.g., 4 Kilobytes or 4 Kb), but with distinctive cache line characteristics. For Direct Memory Access (DMA) reads, the first cache line in the I/O page may be accessed, by a Peripheral Component Interconnect (PCI) Host Bridge, as a cacheable read and all other lines are non-cacheable access (DMA Read with no intent to cache). For DMA writes, the PCI Host Bridge accesses all cache lines as cacheable. The PCI Host Bridge maintains a cache snoop granularity of the I/O page size for data, which means that if the Host Bridge detects a store (invalidate) type system bus operation on any cache line within an I/O page, cached data within that page is invalidated, the Level 1 and Level 2 ((L1/L2) caches continue to treat all cache lines in this page as cacheable). By defining the first line as cacheable, only one cache line need be invalidated on the system bus by the L1/L2 cache in order to cause invalidation of the whole page of data in the PCI Host Bridge. All stores to the other cache lines in the I/O Page can occur directly in the L1/L2 cache without system bus operations, since these lines have been left in the ‘modified’ state in the L1/L2 cache.

摘要翻译： 使用定义为具有大尺寸（例如4千字节或4Kb）但具有鲜明的高速缓存行特征的特殊输入/输出或“I / O”页来改善直接存储器访问和高速缓存性能的方法和装置。 对于直接存储器访问（DMA）读取，I / O页面中的第一个高速缓存行可以由外围组件互连（PCI）主机桥访问，作为可缓存读取，并且所有其他行都是非高速缓存访​​问（DMA读取 没有意图缓存）。 对于DMA写操作，PCI主机桥可以将所有缓存行访问为可缓存的。 PCI主机桥保持数据的I / O页面大小的缓存窥探粒度，这意味着如果主机桥检测到I / O页面中的任何缓存行上的存储（无效）类型的系统总线操作，则缓存数据 该页面无效，级别1和级别2（（L1 / L2）高速缓存继续将该页面中的所有高速缓存行视为可缓存）。 通过将第一行定义为可缓存的，L1 / L2缓存只能在系统总线上只有一条高速缓存行无效，从而导致PCI主机桥中整个数据页的无效。 所有存储到I / O页面中的其他高速缓存行的存储可以直接发生在L1 / L2高速缓存中，而不需要系统总线操作，因为这些行在L1 / L2缓存中保持“修改”状态。

公开(公告)号：US08176339B2

公开(公告)日：2012-05-08

申请号：US11840769

申请日：2007-08-17

申请人： Gary Dean Anderson ,  Hoa Cong Nguyen ,  Thoi Nguyen

发明人： Gary Dean Anderson ,  Hoa Cong Nguyen ,  Thoi Nguyen

IPC分类号： G06F1/32

CPC分类号： G06F1/3209

摘要： A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

摘要翻译： 用于在支持多个虚拟机的处理系统中管理外围连接唤醒信令的方法和系统提供了一种机制，通过该机制，具有系统唤醒能力的外围设备的所有权在虚拟机之间传送。 电源管理事件信号连接到服务处理器输入，该服务处理器输入又传送信号管理程序以将唤醒活动引导到虚拟机最后执行的特定逻辑分区。 管理程序然后可以确定是否唤醒整个系统或其部分，并且可以将电源管理事件引导到适当的虚拟机。 特别地，外设可以是支持Wake-On-LAN功能的以太网适配器。 通过系统功率循环确保的状态初始化是通过控制待机电源的电源，或者在某些情况下通过强制唤醒信令连接的断开/重新连接的指示来提供的。

公开(公告)号：US20080201710A1

公开(公告)日：2008-08-21

申请号：US11840769

申请日：2007-08-17

申请人： Gary Dean Anderson ,  Hoa Cong Nguyen ,  Thoi Nguyen

发明人： Gary Dean Anderson ,  Hoa Cong Nguyen ,  Thoi Nguyen

IPC分类号： G06F9/455

CPC分类号： G06F1/3209

摘要： A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

公开(公告)号：US07415634B2

公开(公告)日：2008-08-19

申请号：US10809554

申请日：2004-03-25

申请人： Gary Dean Anderson ,  Sheldon Ray Bailey ,  Wayne Allan Britson ,  Alongkorn Kitamorn ,  Michael Alan Kobler

发明人： Gary Dean Anderson ,  Sheldon Ray Bailey ,  Wayne Allan Britson ,  Alongkorn Kitamorn ,  Michael Alan Kobler

IPC分类号： G06F11/00

CPC分类号： G06F11/1417 ,  G06F9/4401 ,  G06F11/1482

摘要： A system and method for fast system recovery that bypasses diagnostic routines by disconnecting failed hardware from the system before rebooting. Failed hardware and hardware that will be affected by removal of the failed hardware of the system are disconnected from the system. The system is restarted, and because the failed hardware is disconnected, diagnostic routines may safely be eliminated from the reboot process.

摘要翻译： 用于快速系统恢复的系统和方法，通过在重新启动之前断开系统中的故障硬件，从而绕过诊断程序。 被系统故障硬件拆除影响的硬件和硬件故障将与系统断开连接。 系统重新启动，并且由于发生故障的硬件已断开连接，诊断程序可能会安全地从重启过程中消除。

公开(公告)号：US07346792B2

公开(公告)日：2008-03-18

申请号：US10916974

申请日：2004-08-12

申请人： Gary Dean Anderson ,  Hoa Cong Nguyen ,  Thoi Nguyen

发明人： Gary Dean Anderson ,  Hoa Cong Nguyen ,  Thoi Nguyen

IPC分类号： G06F13/14

CPC分类号： G06F1/3209

摘要： A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

摘要翻译： 用于在支持多个虚拟机的处理系统中管理外围连接唤醒信令的方法和系统提供了一种机制，通过该机制，具有系统唤醒能力的外围设备的所有权在虚拟机之间传送。 电源管理事件信号连接到服务处理器输入，该服务处理器输入又传送信号管理程序以将唤醒活动引导到虚拟机最后执行的特定逻辑分区。 管理程序然后可以确定是否唤醒整个系统或其部分，并且可以将电源管理事件引导到适当的虚拟机。 特别地，外设可以是支持Wake-On-LAN功能的以太网适配器。 通过系统功率循环确保的状态初始化是通过控制待机电源的电源，或者在某些情况下通过强制唤醒信令连接的断开/重新连接的指示来提供的。

公开(公告)号：US07085948B2

公开(公告)日：2006-08-01

申请号：US10422660

申请日：2003-04-24

申请人： Gary Dean Anderson ,  Adam Charles Lange-Pearson ,  Thomas Joseph Warne

发明人： Gary Dean Anderson ,  Adam Charles Lange-Pearson ,  Thomas Joseph Warne

IPC分类号： G06F1/12 ,  G06F1/06 ,  G06F1/14

CPC分类号： G06F1/14

摘要： A method, apparatus and computer program product are provided for implementing time synchronization correction in computer systems. A service processor includes a battery-backed hardware clock, and a hypervisor includes a hypervisor system clock. A common timer resource is accessible by the hypervisor and the service processor. To synchronize the battery-backed hardware clock and the hypervisor system clock, the common timer resource is used to measure the latency in the communication medium between the hypervisor and the service processor. The latency is then added onto the time value received in time of day messages between the hypervisor and the service processor for time synchronization correction in the computer systems.

摘要翻译： 提供了一种在计算机系统中实现时间同步校正的方法，装置和计算机程序产品。 服务处理器包括电池支持的硬件时钟，管理程序包括管理程序系统时钟。 通用计时器资源可由管理程序和服务处理器访问。 为了同步电池支持的硬件时钟和管理程序系统时钟，公共定时器资源用于测量管理程序和服务处理器之间的通信介质中的延迟。 然后将延迟添加到在管理程序和服务处理器之间的时间消息中接收的时间值，以便在计算机系统中进行时间同步校正。