摘要:
Various aspects of the low cost line buffer system allow a reduction in circuitry versus conventional approaches to line buffer design. A plurality of line buffers such that the output of one line buffer in the plurality of line buffers may be coupled to an input of a succeeding line buffer in the plurality of line buffers. A first line buffer in the plurality of line buffers may be coupled to an input write data signal, while the width of a subsequent plurality of line buffers may be less than or equal to the width of the previous line buffers in the plurality of line buffers.
摘要:
A data and phase locking buffer design in a two-way handshake system is provided and may comprise sequentially locking pipelining of data in a synchronized pipeline and draining the synchronized pipeline of the data. The data may be synchronously accepted at a substantially similar time by contiguous pipeline stages that have data to be accepted. A ready signal, which may be processed after being generated by a present pipeline stage of the synchronized pipeline, may be communicated to a subsequent pipeline stage of the synchronized pipeline. An accept signal may be communicated from a present pipeline stage to a previous pipeline stage. A drain signal may be generated for draining the data from the synchronized pipeline. The drain signal may be asserted and deasserted based on end of line information in the data.
摘要:
A synchronized control scheme in a parallel multi-client two-way handshake system is provided and may comprise processing pixels by a plurality of data processing units using at least one shared buffer. The pixels may be communicated to the plurality of data processing units using a centralized and synchronized flow control mechanism. Pixel accept signals may be utilized to communicate the pixels from the shared buffer to the data processing unit, and each pixel accept signal may correspond to a pixel. The pixel accept signal may be generated based on an accept signal from a subsequent pipeline stage to a present pipeline stage in the shared buffer. A generated control signal from the shared buffer to the data processing unit may be used for centralized and synchronized data flow control. A delay may be generated that delays generation of the control signal to handle boundary conditions during processing.