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公开(公告)号：US20130156133A1
公开(公告)日：2013-06-20
申请号：US12990721
申请日：2010-09-08
IPC分类号： H04L25/02
CPC分类号： H04L25/02 , H03M13/1111 , H03M13/1114 , H03M13/1117 , H03M13/1137 , H03M13/114 , H03M13/2957 , H03M13/2972 , H03M13/3905 , H03M13/3972 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6527 , H03M13/653 , H03M13/6541 , H03M13/6544 , H03M13/6552 , H03M13/6555 , H03M13/6566 , H03M13/6569
摘要： A configurable Turbo-LDPC decoder comprising: A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of said decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing said intermediate data, each of said first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of said decoding units to the output and input ports of said first memory, and the second input and output ports of said decoding units to the output and input ports of said second memory.
摘要翻译： 一种可配置的Turbo-LDPC解码器，包括：用于对Turbo和LDPC编码的输入数据进行迭代解码的一组P> 1个软输入软输出解码单元（DP0-DPP-1; DPi），每个所述解码单元 具有用于中间数据的第一（I1i）和第二（I2i）输入端口和第一（O1i）和第二（O2i）输出端口; 用于存储所述中间数据的第一和第二存储器（M1，M2），所述第一和第二存储器中的每一个包括具有相应输入和输出端口的P个独立可读和可写存储块; 以及用于将所述解码单元的第一输入和输出端口连接到所述第一存储器的输出和输入端口以及所述解码单元的第二输入和输出端口连接到所述第一存储器的输出端口和输入端口的可配置交换网络（SN） 第二个记忆
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公开(公告)号：US08879670B2
公开(公告)日：2014-11-04
申请号：US12990721
申请日：2010-09-08
IPC分类号： H04L27/06
CPC分类号： H04L25/02 , H03M13/1111 , H03M13/1114 , H03M13/1117 , H03M13/1137 , H03M13/114 , H03M13/2957 , H03M13/2972 , H03M13/3905 , H03M13/3972 , H03M13/6508 , H03M13/6513 , H03M13/6519 , H03M13/6525 , H03M13/6527 , H03M13/653 , H03M13/6541 , H03M13/6544 , H03M13/6552 , H03M13/6555 , H03M13/6566 , H03M13/6569
摘要： A configurable Turbo-LDPC decoder having A set of P>1 Soft-Input-Soft-Output decoding units (DP0-DPP-1; DPi) for iteratively decoding both Turbo- and LDPC-encoded input data, each of the decoding units having first (I1i) and second (I2i) input ports and first (O1i) and second (O2i) output ports for intermediate data; First and second memories (M1, M2) for storing the intermediate data, each of the first and second memories comprising P independently readable and writable memory blocks having respective input and output ports; and A configurable switching network (SN) for connecting the first input and output ports of the decoding units to the output and input ports of the first memory, and the second input and output ports of the decoding units to the output and input ports of the second memory.
摘要翻译： 一种可配置的Turbo-LDPC解码器，其具有用于迭代地解码Turbo和LDPC编码的输入数据的P> 1个软输入 - 软输出解码单元（DP0-DPP-1; DPi）集合，每个解码单元具有 用于中间数据的第一（I1i）和第二（I2i）输入端口和第一（O1i）和第二（O2i）输出端口; 用于存储中间数据的第一和第二存储器（M1，M2），第一和第二存储器中的每一个包括具有相应输入和输出端口的P个独立可读和可写存储块; 和可配置交换网络（SN），用于将解码单元的第一输入和输出端口连接到第一存储器的输出和输入端口，以及将解码单元的第二输入和输出端口连接到第一存储器的输出和输入端口 第二个记忆
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