公开(公告)号：US08638173B2

公开(公告)日：2014-01-28

申请号：US13296389

申请日：2011-11-15

申请人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

发明人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03L7/00

CPC分类号： H03L7/0891

摘要： A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

摘要翻译： 在保持锁定的同时校准锁相环（PLL）的方法包括在PLL锁定到输入信号的同时检测到PLL中的振荡器的控制信号已经超过阈值。 作为响应，调整振荡器的工作电流以将控制信号返回低于阈值，同时保持锁定到输入信号。 调整工作电流包括缓慢地改变耦合到PLL的校准电路的输出电流，使PLL能够在调节工作电流期间保持对输入信号的锁定。

公开(公告)号：US20130120072A1

公开(公告)日：2013-05-16

申请号：US13296389

申请日：2011-11-15

申请人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

发明人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03L7/095 ,  G06F17/50

CPC分类号： H03L7/0891

摘要： A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

摘要翻译： 在保持锁定的同时校准锁相环（PLL）的方法包括在PLL锁定到输入信号的同时检测到PLL中的振荡器的控制信号已经超过阈值。 作为响应，调整振荡器的工作电流以将控制信号返回低于阈值，同时保持锁定到输入信号。 调整工作电流包括缓慢地改变耦合到PLL的校准电路的输出电流，使PLL能够在调节工作电流期间保持对输入信号的锁定。

公开(公告)号：US20130187717A1

公开(公告)日：2013-07-25

申请号：US13405468

申请日：2012-02-27

申请人： Glenn A. Murphy ,  Nam V. Dang ,  Tirdad Sowlati ,  Xiaohua Kong

发明人： Glenn A. Murphy ,  Nam V. Dang ,  Tirdad Sowlati ,  Xiaohua Kong

IPC分类号： H03F3/16

CPC分类号： H03F3/3022 ,  H03F1/483

摘要： A receiver equalization circuit includes a first output transistor having a gate coupled to an input signal. The receiver equalization circuit may also include a second output transistor having a drain coupled to a drain of the first output transistor. The receiver equalization circuit may also include a resistor coupled between a gate and a drain of the second output transistor to provide a direct current (DC) bias to the gate of the second output transistor. The receiver equalization circuit may further include a feed-through capacitor coupled between the gate of the second output transistor and an input signal source. The feed-through capacitor feeds the input signal to the gate of the second output transistor when a frequency of the input signal is above a predetermined threshold. The feed-through capacitor and the resistor define a signal gain amplification point.

摘要翻译： 接收机均衡电路包括具有耦合到输入信号的栅极的第一输出晶体管。 接收机均衡电路还可以包括具有耦合到第一输出晶体管的漏极的漏极的第二输出晶体管。 接收机均衡电路还可以包括耦合在第二输出晶体管的栅极和漏极之间的电阻器，以向第二输出晶体管的栅极提供直流（DC）偏置。 接收机均衡电路还可以包括耦合在第二输出晶体管的栅极和输入信号源之间的馈通电容器。 当输入信号的频率高于预定阈值时，馈通电容器将输入信号馈送到第二输出晶体管的栅极。 馈通电容和电阻定义了信号增益放大点。