公开(公告)号：US08638173B2

公开(公告)日：2014-01-28

申请号：US13296389

申请日：2011-11-15

申请人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

发明人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03L7/00

CPC分类号： H03L7/0891

摘要： A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

摘要翻译： 在保持锁定的同时校准锁相环（PLL）的方法包括在PLL锁定到输入信号的同时检测到PLL中的振荡器的控制信号已经超过阈值。 作为响应，调整振荡器的工作电流以将控制信号返回低于阈值，同时保持锁定到输入信号。 调整工作电流包括缓慢地改变耦合到PLL的校准电路的输出电流，使PLL能够在调节工作电流期间保持对输入信号的锁定。

公开(公告)号：US20130120072A1

公开(公告)日：2013-05-16

申请号：US13296389

申请日：2011-11-15

申请人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

发明人： Glenn A. Murphy ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03L7/095 ,  G06F17/50

CPC分类号： H03L7/0891

摘要： A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

摘要翻译： 在保持锁定的同时校准锁相环（PLL）的方法包括在PLL锁定到输入信号的同时检测到PLL中的振荡器的控制信号已经超过阈值。 作为响应，调整振荡器的工作电流以将控制信号返回低于阈值，同时保持锁定到输入信号。 调整工作电流包括缓慢地改变耦合到PLL的校准电路的输出电流，使PLL能够在调节工作电流期间保持对输入信号的锁定。

公开(公告)号：US20130187717A1

公开(公告)日：2013-07-25

申请号：US13405468

申请日：2012-02-27

申请人： Glenn A. Murphy ,  Nam V. Dang ,  Tirdad Sowlati ,  Xiaohua Kong

发明人： Glenn A. Murphy ,  Nam V. Dang ,  Tirdad Sowlati ,  Xiaohua Kong

IPC分类号： H03F3/16

CPC分类号： H03F3/3022 ,  H03F1/483

摘要： A receiver equalization circuit includes a first output transistor having a gate coupled to an input signal. The receiver equalization circuit may also include a second output transistor having a drain coupled to a drain of the first output transistor. The receiver equalization circuit may also include a resistor coupled between a gate and a drain of the second output transistor to provide a direct current (DC) bias to the gate of the second output transistor. The receiver equalization circuit may further include a feed-through capacitor coupled between the gate of the second output transistor and an input signal source. The feed-through capacitor feeds the input signal to the gate of the second output transistor when a frequency of the input signal is above a predetermined threshold. The feed-through capacitor and the resistor define a signal gain amplification point.

摘要翻译： 接收机均衡电路包括具有耦合到输入信号的栅极的第一输出晶体管。 接收机均衡电路还可以包括具有耦合到第一输出晶体管的漏极的漏极的第二输出晶体管。 接收机均衡电路还可以包括耦合在第二输出晶体管的栅极和漏极之间的电阻器，以向第二输出晶体管的栅极提供直流（DC）偏置。 接收机均衡电路还可以包括耦合在第二输出晶体管的栅极和输入信号源之间的馈通电容器。 当输入信号的频率高于预定阈值时，馈通电容器将输入信号馈送到第二输出晶体管的栅极。 馈通电容和电阻定义了信号增益放大点。

公开(公告)号：US08839020B2

公开(公告)日：2014-09-16

申请号：US13420800

申请日：2012-03-15

申请人： Jingcheng Zhuang ,  Nam V. Dang ,  Xiaohua Kong ,  Zhi Zhu ,  Tirdad Sowlati ,  Behnam Amelifard

发明人： Jingcheng Zhuang ,  Nam V. Dang ,  Xiaohua Kong ,  Zhi Zhu ,  Tirdad Sowlati ,  Behnam Amelifard

IPC分类号： G06F1/04 ,  G06F1/12 ,  H03L7/00 ,  H04B7/212 ,  H04L12/28 ,  H04J3/06 ,  H04L7/00 ,  H04B1/16 ,  G06F15/16

CPC分类号： H03L7/0807 ,  H03L7/087 ,  H03L7/091 ,  H03L7/14 ,  H04L7/0004 ,  H04L7/033

摘要： A clock/data recovery circuit includes an edge detector circuit operable to receive a serial data burst and to generate a reset signal in response to a first edge of the serial data burst. The clock/data recovery circuit may also include an oscillator coupled to the edge detector circuit. The oscillator locks onto a target data rate prior to receipt of the serial data burst and locks onto a phase of the serial data burst in response to the reset signal. The clock/data recovery circuit may also include a phase detector circuit that receives the serial data burst. The phase detector circuit is coupled to the oscillator. The phase detector circuit adjusts the oscillator to maintain the lock onto the phase of the serial data burst during the serial data burst.

摘要翻译： 时钟/数据恢复电路包括边沿检测器电路，其可操作以接收串行数据脉冲串并且响应于串行数据脉冲串的第一个边沿而产生复位信号。 时钟/数据恢复电路还可以包括耦合到边缘检测器电路的振荡器。 振荡器在接收到串行数据脉冲串之前锁定到目标数据速率上，并响应于复位信号锁定到串行数据脉冲串的相位上。 时钟/数据恢复电路还可以包括接收串行数据突发的相位检测器电路。 相位检测器电路耦合到振荡器。 相位检测器电路调节振荡器以在串行数据突发期间保持锁定到串行数据突发的相位。

公开(公告)号：US08742864B2

公开(公告)日：2014-06-03

申请号：US12939206

申请日：2010-11-04

申请人： Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

发明人： Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03C3/06

CPC分类号： H03L7/1976

摘要： In a particular embodiment, a method includes adjusting an input to a divider on a feedback path of a phase locked loop circuit based on a stored digital value representing a portion of a time-based waveform that is applied to a modulator circuit. The stored digital value is retrieved based on an output of the feedback path.

摘要翻译： 在一个具体实施例中，一种方法包括基于存储的数字值来调节在锁相环电路的反馈路径上的分频器的输入，该数字值表示施加到调制器电路的基于时间的波形的一部分。 基于反馈路径的输出检索存储的数字值。

公开(公告)号：US20130120071A1

公开(公告)日：2013-05-16

申请号：US13294902

申请日：2011-11-11

申请人： Swarna L. Navubothu ,  Cheng Zhong ,  Nam V. Dang ,  Xiaohua Kong

发明人： Swarna L. Navubothu ,  Cheng Zhong ,  Nam V. Dang ,  Xiaohua Kong

IPC分类号： H03L7/00 ,  G06F17/50

CPC分类号： H03L7/0995 ,  H03K3/0315

摘要： A circuit includes a first path including a first transistor and a first current source. The first transistor is responsive to a tuning voltage. The circuit also includes a tuning voltage range extension circuit responsive to the tuning voltage. The tuning voltage range extension circuit is configured to selectively change current supplied by the first path as the tuning voltage exceeds a capacity threshold of the first transistor.

摘要翻译： 电路包括包括第一晶体管和第一电流源的第一路径。 第一晶体管响应调谐电压。 电路还包括响应于调谐电压的调谐电压范围扩展电路。 调谐电压范围扩展电路被配置为当调谐电压超过第一晶体管的容量阈值时选择性地改变由第一路径提供的电流。

公开(公告)号：US20130120036A1

公开(公告)日：2013-05-16

申请号：US13363410

申请日：2012-02-01

申请人： Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

发明人： Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03L7/08

CPC分类号： H03L7/0802 ,  H03L7/0805 ,  H03L7/0807 ,  H03L7/0995 ,  H04L7/0276 ,  H04L7/0338

摘要： A gated voltage controlled oscillator has four identically structured delay cells, each of the delay cells having the same output load by connecting to the same number of inputs of other ones of the delay cells. Optionally a four phase sampling clock selects from the delay cell output and samples, at a four phase sampler, an input signal. Optionally an edge detector synchronizes the phase of the gated voltage controlled oscillator to coincide with NRZ bits. Optionally a variable sampling rate selects different phases from the delay cells to selectively sample NRZ bits at a lower rate. Optionally, a pulse width modulation (PWM) mode synchronizes a phase of the sampling clock to sample PWM symbols and recover encoded bits.

公开(公告)号：US09753479B2

公开(公告)日：2017-09-05

申请号：US13564150

申请日：2012-08-01

申请人： Madjid Hafizi ,  Jie Xu ,  Xiaohua Kong ,  Nam V. Dang

发明人： Madjid Hafizi ,  Jie Xu ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： G05F3/08 ,  H04L25/02

CPC分类号： G05F3/08 ,  H03F2200/03 ,  H04L25/0278 ,  H04L25/028

摘要： A pre-driver circuit generates a driver bias signal based on a swing command, a driver impedance characteristic, and an input signal. A driver receives the driver bias signal and generates, in response, a driver signal having a swing and having an output impedance corresponding to the bias signal. Optionally, the driver receives power from a switchable one of multiple supply rails, according to the swing. Optionally, the driver has voltage controlled resistor elements and the driver bias signal is generated based on the swing command and a replica of the driver voltage controlled resistor elements.

公开(公告)号：US08630821B2

公开(公告)日：2014-01-14

申请号：US13189926

申请日：2011-07-25

申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

IPC分类号： G06F11/30

CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

公开(公告)号：US20130216014A1

公开(公告)日：2013-08-22

申请号：US13401020

申请日：2012-02-21

申请人： Xiaohua Kong ,  Zhi Zhu ,  Nam V. Dang

发明人： Xiaohua Kong ,  Zhi Zhu ,  Nam V. Dang

IPC分类号： H03D3/24

CPC分类号： H03L7/07 ,  H03L7/0805 ,  H03L7/081 ,  H04L7/0025 ,  H04L7/033

摘要： Systems and methods for automatic detection and compensation of frequency offset in point-to-point communication. A burst mode clock and data recovery (CDR) system comprises input data received at a first frequency and a reference clock operating at a second frequency. A master phase-locked loop (PLL) comprising a first gated voltage controlled oscillator (GVCO) is configured to align the phases of reference clock and the input data, and provide phase error information and a recovered clock. A second GVCO is controlled by the recovered clock to sample the input data. A frequency alignment loop comprising a feedback path from the second GVCO to the master PLL is configured to use the phase error information to correct a frequency offset between the first frequency and the second frequency.

摘要翻译： 自动检测和补偿点对点通信中频偏的系统和方法。 突发模式时钟和数据恢复（CDR）系统包括以第一频率接收的输入数据和以第二频率工作的参考时钟。 包括第一门控压控振荡器（GVCO）的主锁相环（PLL）被配置为对准参考时钟和输入数据的相位，并提供相位误差信息和恢复的时钟。 第二个GVCO由恢复的时钟控制，以对输入数据进行采样。 包括从第二GVCO到主PLL的反馈路径的频率对准环路被配置为使用相位误差信息来校正第一频率和第二频率之间的频率偏移。