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公开(公告)号:US07392098B2
公开(公告)日:2008-06-24
申请号:US10522008
申请日:2003-07-18
申请人: Peter John Miller , Andrew Charles Osborne Smith , Michael John Lindsey , Robert John Barnes , David John Allen , Graham Ludar-Smith
发明人: Peter John Miller , Andrew Charles Osborne Smith , Michael John Lindsey , Robert John Barnes , David John Allen , Graham Ludar-Smith
IPC分类号: G05B11/01
CPC分类号: B60G17/0195 , B60G17/0185 , B60G2600/02 , B60G2600/042 , B60G2600/08 , B60G2600/082 , B60G2600/702 , B60G2800/802 , B60W2050/0005 , B60W2050/0292 , B60W2710/02 , B60W2710/10 , G05B9/02 , G05B19/4062 , G05B2219/37632 , G05B2219/50198
摘要: A control system for a load (10), the system comprising a first microprocessor (16) having an output to drive one side of a load (10), a second microprocessor (18) having an output to drive the other side of the load (10), the system being arranged so that when either microprocessor detects a fault in the control of the load (10) the load (10) is switched off.
摘要翻译: 一种用于负载(10)的控制系统,所述系统包括具有用于驱动负载(10)的一侧的输出的第一微处理器(16),具有用于驱动所述负载的另一侧的输出的第二微处理器(18) (10),所述系统被布置成使得当任一微处理器检测到所述负载(10)的控制中的故障时,所述负载(10)被关闭。
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公开(公告)号:US20060122713A1
公开(公告)日:2006-06-08
申请号:US10522008
申请日:2003-07-18
申请人: Peter Miller , Andrew Smith , Michael Lindsey , Robert Barnes , David Allen , Graham Ludar-Smith
发明人: Peter Miller , Andrew Smith , Michael Lindsey , Robert Barnes , David Allen , Graham Ludar-Smith
IPC分类号: G05B11/01
CPC分类号: B60G17/0195 , B60G17/0185 , B60G2600/02 , B60G2600/042 , B60G2600/08 , B60G2600/082 , B60G2600/702 , B60G2800/802 , B60W2050/0005 , B60W2050/0292 , B60W2710/02 , B60W2710/10 , G05B9/02 , G05B19/4062 , G05B2219/37632 , G05B2219/50198
摘要: A control system for a load (10), the system comprising a first microprocessor (16) having an output to drive one side of a load (10), a second microprocessor (18) having an output to drive the other side of the load (10), the system being arranged so that when either microprocessor detects a fault in the control of the load (10) the load (10) is switched off.
摘要翻译: 一种用于负载(10)的控制系统,所述系统包括具有用于驱动负载(10)的一侧的输出的第一微处理器(16),具有用于驱动所述负载的另一侧的输出的第二微处理器(18) (10),所述系统被布置成使得当任一微处理器检测到所述负载(10)的控制中的故障时,所述负载(10)被关闭。
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