公开(公告)号：US20050120184A1

公开(公告)日：2005-06-02

申请号：US11028293

申请日：2005-01-04

Applicant: Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

公开(公告)号：US08090869B2

公开(公告)日：2012-01-03

申请号：US10359878

申请日：2003-02-07

Applicant: Greg Mathews

Inventor： Greg Mathews

IPC: G06F15/173

CPC classification number: H04L12/5601 ,  H04L47/50 ,  H04L47/6215 ,  H04L49/203 ,  H04L49/255 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

Abstract: Priority-biased compound arbitration at a switching fabric ingress. The ingress includes a plurality of ingress queues and a priority-biased arbitration engine configured to arbitrate between the ingress queues. The ingress further includes exit first-in-first-out queues (FIFOs) configured to forward cells from the ingress queues to a switching fabric and a throughput-biased arbitration engine configured to arbitrate between the exit FIFOs.

Abstract translation: 交换矩阵入口处的优先级复合仲裁。 入口包括多个入口队列和被配置为在入口队列之间进行仲裁的优先级偏置仲裁引擎。 所述入口还包括配置为将小区从入口队列转发到交换结构的退出先入先出队列（FIFO）以及被配置为在所述退出FIFO之间仲裁的吞吐量偏移仲裁引擎。