公开(公告)号：US08151176B2

公开(公告)日：2012-04-03

申请号：US12270225

申请日：2008-11-13

申请人： Greg Tsutsui ,  Justin Jones

发明人： Greg Tsutsui ,  Justin Jones

IPC分类号： G06F11/00

CPC分类号： G06F11/1016

摘要： A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.

摘要翻译： 奇偶检验电路，包括微处理器，指令存储器，奇偶检验器，地址捕获器件，连接到微处理器的数据总线，指令存储器和奇偶校验器，以及连接到微处理器的地址总线，指令存储器和 地址捕获设备。 指令存储器向奇偶检验器发送奇偶校验位，并且奇偶校验器将其从地址总线接收的地址与从指令存储器接收的奇偶校验比较。 如果检测到奇偶校验错误，则将错误信号发送到地址捕获设备，并且地址捕获设备捕获地址以便随后存储在诸如闪存的存储设备中。 电路还包括寄存器和看门狗复位装置，其有助于在微处理器的命令下的系统电平复位。

公开(公告)号：US20100122150A1

公开(公告)日：2010-05-13

申请号：US12270225

申请日：2008-11-13

申请人： Greg Tsutsui ,  Justin Jones

发明人： Greg Tsutsui ,  Justin Jones

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： G06F11/1016

摘要： A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.

摘要翻译： 奇偶检验电路，包括微处理器，指令存储器，奇偶检验器，地址捕获器件，连接到微处理器的数据总线，指令存储器和奇偶校验器，以及连接到微处理器的地址总线，指令存储器和 地址捕获设备。 指令存储器向奇偶检验器发送奇偶校验位，并且奇偶校验器将其从地址总线接收的地址与从指令存储器接收的奇偶校验比较。 如果检测到奇偶校验错误，则将错误信号发送到地址捕获设备，并且地址捕获设备捕获地址以便随后存储在诸如闪存的存储设备中。 电路还包括寄存器和看门狗复位装置，其有助于在微处理器的命令下的系统电平复位。