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    Exercise device
    1.
    外观设计
    Exercise device 有权

    公开(公告)号：USD1004717S1

    公开(公告)日：2023-11-14

    申请号：US29828445

    申请日：2022-02-25

    申请人： Tyler Jones ,  Justin Jones ,  Vincent Pangallo

    设计人： Tyler Jones ,  Justin Jones ,  Vincent Pangallo

    摘要： FIG. 1 is a front isometric view of an exercise device in accordance with a first embodiment of the present invention;
    FIG. 2 is a top plan view of the exercise device illustrated in FIG. 1;
    FIG. 3 is a front elevation view of the exercise device illustrated in FIG. 1, wherein the rear elevation view is the same;
    FIG. 4 is a first side elevation view of the exercise device illustrated in FIG. 1, wherein the second side elevation view is the same;
    FIG. 5 is a bottom plan view of the exercise device illustrated in FIG. 1;
    FIG. 6 is a front isometric view of an exercise device in accordance with a second embodiment of the present invention;
    FIG. 7 is a top plan view of the exercise device illustrated in FIG. 6;
    FIG. 8 is a front elevation view of the exercise device illustrated in FIG. 6, wherein the rear elevation view is the same;
    FIG. 9 is a first side elevation view of the exercise device illustrated in FIG. 6, wherein the second side elevation view is the same;
    FIG. 10 is a bottom plan view of the exercise device illustrated in FIG. 6;
    FIG. 11 is a front isometric view of an exercise device in accordance with a third embodiment of the present invention;
    FIG. 12 is a top plan view of the exercise device illustrated in FIG. 11;
    FIG. 13 is a front elevation view of the exercise device illustrated in FIG. 11, wherein the rear elevation view is the same;
    FIG. 14 is a first side elevation view of the exercise device illustrated in FIG. 11, wherein the second side elevation view is the same; and,
    FIG. 15 is a bottom plan view of the exercise device illustrated in FIG. 11.

    Methods, data storage devices and systems having variable size ECC page size
    3.
    发明授权
    Methods, data storage devices and systems having variable size ECC page size 有权
    方法，具有可变大小ECC页面大小的数据存储设备和系统

    公开(公告)号：US08898548B1

    公开(公告)日：2014-11-25

    申请号：US13594696

    申请日：2012-08-24

    申请人： Rodney N. Mullendore ,  Radoslav Danilak ,  Justin Jones ,  Andrew J. Tomlin

    发明人： Rodney N. Mullendore ,  Radoslav Danilak ,  Justin Jones ,  Andrew J. Tomlin

    IPC分类号： H03M13/00

    CPC分类号： H03M13/353 ,  G06F11/1048

    摘要： A data storage device may comprise an array of flash memory devices and a controller coupled thereto, configured to program and read data from the array responsive to received data access commands. The array may comprise a plurality of blocks, each comprising a plurality of flash pages (F-Pages), each of which comprising an integer number of one or more error correcting code pages (E-Pages), at least some of which comprising a data portion and an error correction code (ECC) portion. The controller may be configured to store a plurality of logical pages (L-Pages) in one or more of the plurality of E-Pages, at least some being unaligned with boundaries of the E-Pages; and to adjust, in at least one of the blocks, the size of the ECC portion and correspondingly adjust the size of the data portion of the E-Pages.

    摘要翻译： 数据存储设备可以包括闪存器件阵列和耦合到其上的控制器，被配置为响应于接收到的数据访问命令对阵列进行编程和读取数据。 阵列可以包括多个块，每个块包括多个闪存页（F页），每个闪存页包括整数数量的一个或多个纠错码页（E-Pages），其中至少一些包括 数据部分和纠错码（ECC）部分。 控制器可以被配置为将多个逻辑页面（L页面）存储在多个E页面中的一个或多个中，至少一些与E页面的边界不对齐; 并且在至少一个块中调整ECC部分的大小并相应地调整E-Pages的数据部分的大小。

    CPU instruction RAM parity error procedure
    4.
    发明授权
    CPU instruction RAM parity error procedure 失效
    CPU指令RAM奇偶校验错误程序

    公开(公告)号：US08151176B2

    公开(公告)日：2012-04-03

    申请号：US12270225

    申请日：2008-11-13

    申请人： Greg Tsutsui ,  Justin Jones

    发明人： Greg Tsutsui ,  Justin Jones

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1016

    摘要： A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.

    摘要翻译： 奇偶检验电路，包括微处理器，指令存储器，奇偶检验器，地址捕获器件，连接到微处理器的数据总线，指令存储器和奇偶校验器，以及连接到微处理器的地址总线，指令存储器和 地址捕获设备。 指令存储器向奇偶检验器发送奇偶校验位，并且奇偶校验器将其从地址总线接收的地址与从指令存储器接收的奇偶校验比较。 如果检测到奇偶校验错误，则将错误信号发送到地址捕获设备，并且地址捕获设备捕获地址以便随后存储在诸如闪存的存储设备中。 电路还包括寄存器和看门狗复位装置，其有助于在微处理器的命令下的系统电平复位。

    CPU INSTRUCTION RAM PARITY ERROR PROCEDURE
    5.
    发明申请
    CPU INSTRUCTION RAM PARITY ERROR PROCEDURE 失效
    CPU指令RAM奇偶校验错误程序

    公开(公告)号：US20100122150A1

    公开(公告)日：2010-05-13

    申请号：US12270225

    申请日：2008-11-13

    申请人： Greg Tsutsui ,  Justin Jones

    发明人： Greg Tsutsui ,  Justin Jones

    IPC分类号： H03M13/09 ,  G06F11/10

    CPC分类号： G06F11/1016

    摘要： A parity checking circuit which includes a microprocessor, instruction memory, a parity checker, an address capture device, a data bus connected to the microprocessor, the instruction memory and the parity checker, and an address bus connected to the microprocessor, the instruction memory and the address capture device. The instruction memory sends a parity bit to the parity checker, and the parity checker compare an address it receives from the address bus to the parity bit it receives from the instruction memory. If a parity error is detected, an error signal is sent to the address capture device and the address capture device captures the address for subsequent storage in a storage device, such as flash memory. The circuit also includes registers and a watchdog reset device which facilitates a system level reset at the command of the microprocessor.

    摘要翻译： 奇偶检验电路，包括微处理器，指令存储器，奇偶检验器，地址捕获器件，连接到微处理器的数据总线，指令存储器和奇偶校验器，以及连接到微处理器的地址总线，指令存储器和 地址捕获设备。 指令存储器向奇偶检验器发送奇偶校验位，并且奇偶校验器将其从地址总线接收的地址与从指令存储器接收的奇偶校验比较。 如果检测到奇偶校验错误，则将错误信号发送到地址捕获设备，并且地址捕获设备捕获地址以便随后存储在诸如闪存的存储设备中。 电路还包括寄存器和看门狗复位装置，其有助于在微处理器的命令下的系统电平复位。

    SPLICED WIRE ELECTRICAL JUNCTION BOX
    6.
    发明公开
    SPLICED WIRE ELECTRICAL JUNCTION BOX 审中-公开

    公开(公告)号：US20240120721A1

    公开(公告)日：2024-04-11

    申请号：US17962448

    申请日：2022-10-07

    申请人： Justin Jones ,  Daniel Bonomo

    发明人： Justin Jones ,  Daniel Bonomo

    IPC分类号： H02G3/08 ,  H02G3/14

    CPC分类号： H02G3/083 ,  H02G3/14

    摘要： An example includes a first box half with a top first half bushing, a bottom first half bushing, and a second box half with a top second half bushing, and a bottom second half bushing, and the first box half and the second box half are separate and are affixed to one another by a hinge with a rotating axis. The box in a closed position provides a way to shield and protect a wire splice.

    EXERCISE DEVICE
    7.
    发明公开
    EXERCISE DEVICE 审中-公开

    公开(公告)号：US20240001191A1

    公开(公告)日：2024-01-04

    申请号：US18114117

    申请日：2023-02-24

    申请人： Tyler Jones ,  Justin Jones ,  Vincent Pangallo

    发明人： Tyler Jones ,  Justin Jones ,  Vincent Pangallo

    IPC分类号： A63B21/06 ,  A63B21/00

    CPC分类号： A63B21/0604 ,  A63B21/4035

    摘要： An exercise device has a generally spheroidal body having a top, a bottom, a first side, a second side, a front, and a rear, a first handle extending outwardly from the first side, the first handle comprising a grip spaced from the body; and a second handle extending outwardly from the second side, the second handle comprising a grip spaced from the body, wherein the first and second handles extend upwardly towards the top of said body at an angle relative to a horizontal plane through the body. Exercise devices of different masses may have different sized bodies, but have approximately the same total width from handle to handle.

    Methods and systems for using multiple data sets to analyze performance metrics of targeted companies
    10.
    发明申请
    Methods and systems for using multiple data sets to analyze performance metrics of targeted companies 有权
    使用多个数据集分析目标公司绩效指标的方法和系统

    公开(公告)号：US20070265908A1

    公开(公告)日：2007-11-15

    申请号：US10972179

    申请日：2004-10-22

    申请人： Anthony Berkman ,  Seth Goldstein ,  Justin Jones

    发明人： Anthony Berkman ,  Seth Goldstein ,  Justin Jones

    IPC分类号： G06F11/34

    CPC分类号： G06Q30/0201 ,  G06Q10/06393 ,  G06Q30/02 ,  G06Q40/00

    摘要： New and improved methods and systems for modeling the performance of selected company metrics. Multiple, non-traditional sets of objective data along with mathematical analytical techniques are used to provide transparency and visibility into company performance relating to the particular metrics. Company inflection points and changes in strategy may be identified. The performance of a company and/or the performance of a selected industry or industry sector may be analyzed.

    摘要翻译： 新的和改进的方法和系统，用于对所选公司指标的绩效进行建模。 使用多个非传统的客观数据集以及数学分析技术来提供与特定指标相关的公司绩效的透明度和可见度。 可以确定公司的拐点和策略的变化。 可以分析公司的表现和/或选定的行业或行业的表现。